Data recovery circuit for minimizing power consumption by...

Details Data recovery circuit for minimizing power consumption by... Data recovery circuit for minimizing power consumption by...

2006-06-27

2006-06-27

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C714S700000, C714S744000

Reexamination Certificate

active

07069481

ABSTRACT:
A data recovery circuit has a phase-locked loop for generating a plurality of clock signals; an oversampling unit for non-integer times oversampling serial data, and outputting the oversampled result as sample data formed of a plurality of bits; a pattern detector for receiving the sample data, and generating a pattern signal; a state accumulator for receiving the pattern signal, accumulating the frequency of occurrence of the pattern signal, and outputting the pattern signal having the highest frequency of occurrence as a state signal; a state selector for receiving the state signal, and generating a state selection signal for selecting bits at predetermined positions in the sample data; and a data selector for receiving the sample data, selecting bits of the sample data in response to the state selection signal, and outputting the selected bits as recovered data formed of a plurality of bits.

REFERENCES:
patent: 3946379 (1976-03-01), Lippman
patent: 4109236 (1978-08-01), Besenfelder et al.
patent: 5313496 (1994-05-01), de Goede
patent: 5850422 (1998-12-01), Chen
patent: 6272193 (2001-08-01), Eglit
patent: 6801591 (2004-10-01), Frencken
patent: 6847789 (2005-01-01), Savoj

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