Data outputting circuit for semiconductor memory device

Details Data outputting circuit for semiconductor memory device Data outputting circuit for semiconductor memory device

2000-10-06

2002-03-05

Dinh, Son T. (Department: 2812)

Static information storage and retrieval

Read/write circuit

Precharge

C365S189110, C365S207000, C365S208000, C365S189050

Reexamination Certificate

active

06353567

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor memory device, more particularly to a data outputting circuit for reading data from a semiconductor memory device.
2. Description of the Prior Art
FIG. 1
illustrates a schematic block diagram of a conventional data outputting circuit incorporated in a semiconductor memory device, which shows data transmitting path. The data outputting circuit includes a data sense amplifier
11
and an output buffer
12
. A switch circuit
10
formed of an address select column consisting of a plurality of NMOS transistors, sets between a memory device and the outputting circuit. The switching circuit
10
is connected to a pair of data lines DL and DL′. Cell information is read from one of memory cells in the memory device. The cell information is then provided as a pair of complementary data to the data outputting circuit of the memory device via the switching circuit
10
and the data lines DL and DL′.
In general, the respective signals of the data lines DL and DL′ formed of the pair of complementary data from the selected memory cell are directly transmitted to the data sense amplifier
11
for sensing signal difference therebetween and amplifying these two respective signals. Thereafter, the two respective signals are received and stored in the output buffer
12
for output. However, in case that there is large loading existing both in the two data lines DL and DL′ due to the long data lines, it takes a longer time to generate sufficient signal difference between the data lines DL and DL′ to enable the data sense amplifier
11
sensing the exact signal difference and make right action. Hence the sensing time of the data sense amplifier
11
will be delayed and the speed for data output is significantly reduced.
Accordingly, it is desirable to provide a data outputting circuit for semiconductor memory device, which can alleviate long-time sensing effect of the data sense amplifier resulting from large loading existing in the data lines.
SUMMARY OF THE INVENTION
It is one object of the present invention to provide a data outputting circuit for semiconductor memory device, in which a data pre-sensing unit, respectively coupled to a position in a first data line having one half loading and a position in a second data line having one half loading. One of respective signals of the first data line and the second data line is grounded and the other of the respective signals is maintained by means of the data pre-sensing unit, so that signal difference between the first data line and the second data line is amplified after passing through the data pre-sensing unit, and is sufficient to facilitate sensing of a data sense amplifier, even though there exists large loading both in the first data line and the second data line.
It is another object of the present invention to provide a data outputting circuit for a semiconductor memory device, which comprises a data pre-sensing unit respectively coupled to a first data line and a second data line before the two data lines transmit to a data sense amplifier. The data pre-sensing unit amplifies one of respective signals of the first data line and the second data line, while maintaining the other of the respective signals, and thereby amplifying signal difference between the first data line and the second data line. Therefore, the long-time sensing effect of the data sense amplifier for sensing the signal difference between the first data line and the second data line due to the fact that large loading existing in the two data lines is eliminated.
In order to achieve the above objects, the present invention provides a data outputting circuit for a semiconductor memory device, comprising a pre-charging unit, a data pre-sensing unit made up of a first sense amplifier, a second sense amplifier and an inverter, a data sense amplifier and an output buffer. The data pre-sensing unit is respectively coupled to a position in a first data line having one half loading and a position in a second data line having one half loading. One of the respective signals of the first data line and the second data line is amplified and the other of the respective signals is maintained after passing through the data pre-sensing unit. Thereby, the signal difference between the first data line and the second data line is amplified by means of the data pre-sensing unit and is sufficient to facilitate sensing of the data sense amplifier, even though there exists large loading both in the first data line and the second data line.


REFERENCES:
patent: 4685087 (1987-08-01), Shah
patent: 5381374 (1995-01-01), Shiraishi et al.
patent: 5553029 (1996-09-01), Reohr et al.
patent: 5959918 (1999-09-01), Arimoto
patent: 5982689 (1999-11-01), Takahashi
patent: 6023436 (2000-02-01), Han

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