Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-12-20
2004-11-30
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189080, C365S189110
Reexamination Certificate
active
06826089
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims priority from Korean Patent Application No. 2002-32603, filed on Jun. 11, 2002, the contents of which are hereby incorporated by reference herein in their entirety for all purposes as if fully set forth herein.
BACKGROUND AND SUMMARY
1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a data output driver and data output method for minimizing data output time (tQ) variation caused by various data patterns.
2. Description
High integration, low power consumption, and high speed are the trends of semiconductor memory devices today. That is, semiconductor memory devices that process more data at a higher speed with less power consumption are needed.
As a result, for high speed operation of a semiconductor memory device, a synchronous dynamic random access memory (SDRAM) synchronized with a system clock has been developed.
Also, more recently, according to demands for a higher operation speed, a dual data rate (DDR) synchronous DRAM and a RAMBUS® DRAM have been developed that input or output data synchronized both at the rising edge and the falling edge of a system clock.
FIG. 1
is a timing diagram showing variations in data output time (tQ).
Referring to
FIG. 1
, it is preferable that both in the synchronous DRAM and RAMBUS® DRAM, the output time (tQ) of each data item through a plurality of input and/or output pads synchronized to a system clock (CLOCK) is almost constant.
Here, tQ=0 denotes a case when the center of data (D) coincides with the rising edge of the system clock (CLOCK), and tQ=&Dgr;t denotes a case when the center of data is output after being delayed for a predetermined time from the rising edge of the system clock (CLOCK).
Therefore, when the output time (tQ) of each data item through the plurality of input and/or output pads is different from each other, the performance of the semiconductor device is degraded.
Also, in testing RAMBUS® DRAMs, semiconductor device manufacturers test the data output time (tQ) through input and/or output pads according to predetermined specifications, and RAMBUS® DRAMs that do not satisfy the specifications are treated as poor quality products. As a result, the yield of semiconductor chips may decrease.
To address these problems, it is an object of the present invention to provide a data output driver and data output method that minimizes data output time (tQ) variations caused by data patterns that are input.
According to one aspect of the invention, a data output driver adapted to drive data that is input through an input terminal, to an output terminal, comprises: an intermediate node; a first driver connected between the output terminal and the intermediate node, the first driver having a control terminal and being adapted to provide a current path between the intermediate node and the output terminal in response to an enable signal input to the control terminal; a second driver connected between the intermediate node and a lower supply voltage (e.g., ground) and being adapted to drive the data that is input to the input terminal to the output terminal through the intermediate node in a data read operation; and a voltage control circuit connected between the intermediate node and the lower supply voltage, wherein the voltage control circuit has a control terminal and is adapted to cause at least a portion of the current of the intermediate node to flow to the lower supply voltage in response to a control signal input to the control terminal.
When the data output driver performs a data read operation, beneficially the voltage control circuit is adapted to maintain a voltage swing at the intermediate node at a substantially constant level during the data read operation.
According to another aspect of the invention, a data output driver having an input terminal and an output terminal, comprises: a first current path provided between the output terminal and an intermediate node when a data read operation is performed; a driver adapted to drive data that is input through the input terminal, to the output terminal through the intermediate node in the data read operation; and a second current path provided between the intermediate node and a lower supply voltage (e.g., ground) during the data read operation.
Beneficially, the second current path causes a portion of a charging current, that flows into the intermediate node through the first current path, to flow into the lower supply voltage.
According to yet another aspect of the invention, a data output driver adapted to drive data that is input through an input terminal, to an output terminal, comprises: an intermediate node; a first transistor connected between the output terminal and the intermediate node, the first transistor including a control terminal to which an enable signal is input; a second transistor connected between the intermediate node and a lower supply voltage (e.g., ground), the second transistor including the input terminal through which the data is input; and a third transistor connected between the intermediate node and the lower supply voltage, the third transistor including a control terminal to which a control signal is input.
Beneficially, the enable signal is activated when the data output driver performs a data read operation. Beneficially, the control signal is activated when the data output driver performs a data read operation. When the data output driver performs a data read operation, it is preferable that the third transistor discharges to the lower supply voltage a portion of a current flowing into the intermediate node, to maintain a voltage swing at the intermediate node at a substantially constant level. Beneficially, the first through the third transistors are NMOS transistors.
According to still another aspect of the invention, a data output driver comprises: an output terminal; an intermediate node; a first transistor connected between the output terminal and the intermediate node, and including a gate to which an enable signal is input; a second transistor connected between the intermediate node and a lower supply voltage (e.g., ground), and including a gate to which data is input; and a third transistor connected between the intermediate node and the lower supply voltage, and comprising a gate to which a control signal is input.
Beneficially, when the data output driver performs a data read operation, the third transistor causes a predetermined amount of a current flowing into the intermediate node through the first transistor to flow to the lower supply voltage, maintaining a voltage swing at the intermediate node at a substantially constant level during the data read operation.
According to a further aspect of the invention, in a data output driver having an input terminal, an output terminal, and an intermediate node, a method of outputting to the output terminal data that is input to the input terminal comprises: providing a current path between the intermediate node and a lower supply voltage (e.g., ground) to maintain a voltage swing voltage at the intermediate node at a substantially constant level during a data read operation; and outputting through the intermediate node to the output terminal the data that is input to the input terminal.
In connecting the intermediate node to a ground, it is beneficial that in response to a data read signal a predetermined amount of a charging current flowing into the intermediate node is caused to flow into the lower supply voltage, so that the voltage swing of the intermediate node is kept constant.
In yet a further aspect of the invention, in a data output driver having an input terminal, an output terminal, and an intermediate node, a method of outputting to the output terminal data that is input to the input terminal comprises: maintaining a voltage swing at the intermediate node at a substantially constant level during a data read operation; and outputting the data which is input through the input terminal, to the output terminal through the intermediate no
Elms Richard
Nguyen Hien
Samsung Electronics Co,. Ltd.
Volentine Francos & Whitt PLLC
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