Data output circuit and method in DDR synchronous...

Details Data output circuit and method in DDR synchronous... Data output circuit and method in DDR synchronous...

2008-05-20

2008-05-20

Nguyen, Tanh Q (Department: 2182)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189011, C365S189020, C365S189040, C365S189080, C365S220000, C365S221000, C365S230020, C365S230040, C365S230080, C710S065000, C710S071000, C711S104000, C711S105000, C711S168000

Reexamination Certificate

active

07376021

ABSTRACT:
Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

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English language abstract of Korean Publication No. 2000-0044572.
English language abstract of Korean Publication No. 2001-0048248.

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