Data output buffers and methods having a clamp function

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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Details

36518906, 365203, 326 88, G11C 700

Patent

active

056383282

ABSTRACT:
An integrated circuit data output buffer which may be used in an integrated circuit memory device, includes a data output circuit which is responsive to a data input signal to generate a data output signal, using a boosting data signal. A pulse generator generates a pulse in response to a control signal. A power supply sensing circuit is connected to the pulse generator, and generates a power supply voltage sensing signal in response to the pulse. A clamp circuit is connected to the power supply voltage sensing circuit and to the data output circuit, to clamp the boosting power signal after a predetermined time in response to the power supply voltage sensing signal. Accordingly, output data is buffered by generating a pulse in response to a control signal and generating a power supply voltage sensing signal in response to the pulse. A boosting data signal is clamped after a predetermined time in response to the power supply voltage sensing signal and a data output signal is generated in response to a data input signal, using the clamped boosting data signal. In an integrated circuit memory device, the control signal may be a row address strobe signal.

REFERENCES:
patent: 5241502 (1993-08-01), Lee et al.
patent: 5268600 (1993-12-01), Yeu
patent: 5469385 (1995-11-01), Smith et al.

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