Data output buffer circuit and semiconductor memory device...

Details Data output buffer circuit and semiconductor memory device... Data output buffer circuit and semiconductor memory device...

2011-04-19

2011-04-19

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189080, C365S194000

Reexamination Certificate

active

07929357

ABSTRACT:
The example embodiments provide a data output buffer circuit which includes a pre-driver configured to adjust a slew rate of an input signal, a main driver configured to output signal supplied from the pre-driver, and a ZQ calibration circuit configured to control the pre-driver so as to decrease the slew rate when an operation voltage increases, and increase the slew rate when the operation voltage is decreased.

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patent: 6646483 (2003-11-01), Shin
patent: 2003/0025541 (2003-02-01), Humphrey et al.
patent: 2003/0042953 (2003-03-01), Shin
patent: 2004/0165449 (2004-08-01), Pan
patent: 2005/0231251 (2005-10-01), Im et al.
patent: 2007/0069784 (2007-03-01), Shin et al.
patent: 2007/0126477 (2007-06-01), Rho
patent: 2007-166603 (2007-06-01), None
patent: 10-0640782 (2006-10-01), None
patent: 10-2007-0036554 (2007-04-01), None
patent: 10-0693922 (2007-06-01), None

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