Data line precharging circuit of a semiconductor memory device

Details Data line precharging circuit of a semiconductor memory device Data line precharging circuit of a semiconductor memory device

2001-06-06

2003-04-22

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S233100

Reexamination Certificate

active

06552942

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2000-066543, filed on Nov. 9, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention generally relates to semiconductor memory devices and, more specifically, to a semiconductor memory device capable of read out normally data with a low power supply voltage.
BACKGROUND OF THE INVENTION
FIG. 1
is a block diagram showing a data output construction in semiconductor memory device according to the conventional art.
Referring to
FIG. 1
, a plurality of registers R
0
~Rn correspond to a single data line DL, and respectively store data bits read from a data storage region or a memory cell array. The registers R
0
~Rn are connected to the data line DL through corresponding selection transistors M
0
~Mn which are respectively controlled by corresponding selection signals SEL
0
~SELn. Here, the selection signals SEL
0
~SELn are sequentially activated in accordance with decoded results of address.
An inverter I
11
is connected to the data line DL. Inverter I
11
serves as a driver for transferring the data of the data line DL to an output terminal.
In a circuit operation, it is assumed that one, e.g., SEL
1
, of the selection signals SEL
0
~SELn is selected. Selections is by controlling the voltages. The selected signal SEL
1
has power supply voltage Vdd, while the other signals SEL
0
and SEL
2
~SELn have ground voltage. Thus, the N-channel metal oxide semiconductor (NMOS) transistor M
1
is turned on, while the NMOS transistors M
0
, and M
2
~Mn are turned off. Accordingly, a data bit held in the register R
1
is transferred to the data line DL through the turned-on NMOS transistor M
1
.
Transfer is as follows: If the data bit held in the register R
1
is “0”, the inverter I
11
provides data bit DOUT of “1” by responding to a discharged potential of the data line DL. If the stored data bit in the register R
1
is “1”, the potential of the data line DL is Vdd−Vth. Vth is a threshold voltage of the NMOS transistor. The difference is because the power supply voltage corresponding to the data bit “1” is dropped by an amount equaling the threshold voltage Vth of the NMOS transistor M
1
.
A problem in the prior art arises at high speeds. In the circuit of
FIG. 1
, when the next decoding output is activated fast, it will be before the prior output has become inactive. This means that the activation periods of two successive selection signals overlap.
As a result of overlapping, output terminals of the registers corresponding to the signals become connected to each other, resulting in losing the data bits stored in the registers. And then, if the stored data bit is “1”, the potential of the data line DL becomes Vdd−Vth, for the reason described above. In the case that the potential of the data line DL is lower than a trigger voltage of the inverter I
11
by the lowered power supply voltage Vdd, the data cannot read out normally.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor memory device capable of normally reading out data even at a low power supply voltage level.
It is another object of the present invention to provide a semiconductor memory device capable of preventing data register selection signals from overlapping.
In order to attain the above objects, according to an aspect of the present invention, there is provided a semiconductor memory device having at least one data line, a plurality of registers for storing data bits, a plurality of switch elements for transferring the stored data bits to the data line. The device includes a precharge circuit connected to the data line, for precharging the data line to a power supply voltage.
According to the semiconductor memory device of the present invention, the data can be read out even in low power supply voltage by precharging the data line to the power supply voltage.
Additional features and advantages of the invention will be understood from the following description and drawings, in which:


REFERENCES:
patent: 5671181 (1997-09-01), Hatsuda
patent: 6023436 (2000-02-01), Han
patent: 6198679 (2001-03-01), Nakasu et al.

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