Data latch circuit having non-volatile memory cell equipped with

Details Data latch circuit having non-volatile memory cell equipped with Data latch circuit having non-volatile memory cell equipped with

1994-02-23

1995-06-27

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365185, 365200, 36523008, G11C 1140, G11C 1602

Patent

active

054285712

ABSTRACT:
A data latch circuit comprises a non-volatile memory cell having its threshold voltage changed in accordance with data to be stored therein, and a latch circuit. The cell has a transistor for writing data and a transistor for reading data. The writing and reading transistors has a common floating gate. The reading transistor has a threshold voltage lower than the writing transistor. During normal operation, a ground potential is applied to the control gate of the reading transistor. The latch circuit latches data in accordance with whether the non-volatile memory cell is in the on-state or off-state.

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