Data latch circuit having non-volatile memory cell

Details Data latch circuit having non-volatile memory cell Data latch circuit having non-volatile memory cell

1992-07-24

1994-05-10

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365154, 365185, 36518909, 365200, 36523008, G11C 1140, G11C 1710

Patent

active

053114701

ABSTRACT:
A data latch circuit comprises a non-volatile memory cell having its threshold voltage changed in accordance with data to be stored therein, and a latch circuit. The cell has a transistor for writing data and a transistor for reading data. The writing and reading transistors has a common floating gate. The reading transistor has a threshold voltage lower than the writing transistor. During normal operation, a ground potential is applied to the control gate of the reading transistor. The latch circuit latches data in accordance with whether the non-volatile memory cell is in the on-state or off-state.

REFERENCES:
patent: 4532611 (1985-07-01), Countryman, Jr.
patent: 4573144 (1986-02-01), Countryman, Jr.
patent: 4621346 (1986-11-01), McAdams
patent: 4803659 (1989-02-01), Hallenbeck
IEEE, J. of Solid State Circuits, vol. SC-21, No. 5; Oct. 1986, pp. 775-784, J. Pathak et al "A 19-ns 250-mW CMOS Erasable Programmable Logic Device".
1985 IEEE International Solid-State Circuit Conference; pp. 162-163, S. Pathak et al. "a 25ns 16K CMOS PROM Using a 4-Transistor Cell".

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