Data input circuit and method for synchronous semiconductor...

Details Data input circuit and method for synchronous semiconductor... Data input circuit and method for synchronous semiconductor...

2006-03-21

2006-03-21

Mai, Son (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S194000, C365S219000, C365S233100

Reexamination Certificate

active

07016237

ABSTRACT:
A circuit for receiving data to be written in a synchronous semiconductor memory device, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of transitions of the internal strobe signal and for outputting an indicating signal upon counting the end of a string of internal strobe signals; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock.

REFERENCES:
patent: 5223833 (1993-06-01), Akata
patent: 6407963 (2002-06-01), Sonoda et al.
patent: 6819616 (2004-11-01), La et al.

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