Data holding circuit

Details Data holding circuit Data holding circuit

1996-10-29

1998-05-26

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365154, 365156, 365190, G11C 700

Patent

active

057577021

ABSTRACT:
A memory cell includes a first inverter and a second inverter connected with each other through the output node of one of the inverters and the input node of the other inverter, and first and second transistors. Each of the transistors connected with a word line at its gate electrode is interposed between one of a bit line pair and each memory node. This data holding circuit includes an element for increasing a memory cell supply potential for driving the pair of inverters to be higher than a supply potential applied to peripheral circuits, or an element for decreasing a ground voltage for driving the pair of inverters to be lower than a ground voltage applied to the peripheral circuits.

REFERENCES:
patent: 4872141 (1989-10-01), Plus et al.
patent: 5040146 (1991-08-01), Mattausch et al.
patent: 5367482 (1994-11-01), Guo et al.
patent: 5438538 (1995-08-01), Hashimoto
1995 Symposium on VLSI Circuits Digest of Technical Papers "Driving Source-Line (DSL) Cell Architecture for Sub-1-V High-Speed Low-Power Applications", Hiroyuki Mizuno and Takahiro Nagano, pp. 25-26.

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