Damascene patterning of barrier layer metal for C4 solder bumps

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S613000, C257SE21508, C257SE21514

Reexamination Certificate

active

07541272

ABSTRACT:
A system and method for forming a novel C4 solder bump for BLM (Ball Limiting Metallurgy) includes a novel damascene technique is implemented to eliminate the Cu undercut problem and improve the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP. Only bottom layers of the barrier metal stack are patterned by a wet etching. The wet etch time for the Cu-based metals is greatly reduced resulting in a reduced undercut. This allows the pitch of the C4 solder bumps to be reduced. An alternate method includes use of multiple vias at the solder bump terminal.

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patent: 2005/0285116 (2005-12-01), Wang
patent: 2006/0278982 (2006-12-01), Solo De Zaldivar
patent: 2007/0018322 (2007-01-01), Park et al.

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