Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-01-04
2001-12-18
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S624000, C438S633000, C438S638000, C438S700000
Reexamination Certificate
active
06331481
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to damascene processing and, in particular, to a method of providing a low dielectric constant, ∈, material to an intermetal dielectric containing planarized in-laid wiring. The method of the present invention eliminates integration problems normally associated when materials having a low dielectric constant are to be used in conjunction with dielectric materials having a dielectric constant of 4.0 or higher. The present invention also relates to damascene structures, single and dual, which are produced using the method of the present invention. Since the method of the present invention is employed in fabricating damascene structures, the fabricated structures do not have any integration problems associated therewith. Moreover, the single and dual damascene structures of the present invention have reduced cross-talk and stray capacitance as compared to prior art damascene structures.
BACKGROUND OF THE INVENTION
Dual damascene is currently being used in sub-0.25 micron logic and 1-gigabyte dynamic random access memory (DRAM) cells and beyond technologies to reduce cost of ownership and improve via reliability. In addition, copper wiring is employed in sub-0.25 micron generation back end of the line (BEOL) wiring to reduce the wiring resistance and to meet the BEOL resistance capacitance (RC) delay performance requirements. The initial CMOS programs used SiO
2
as a dielectric material. However, as chip function integration increases, back end wiring densities also increase. Because of this, there exists a greater need for intralevel insulators having a dielectric constant lower than Sio
2
. SiO
2
is presently the insulator of choice since the same has relatively good film properties.
The incorporation of low dielectric materials into wiring structures is crucial in order to reduce delays due to cross-talk and stray capacitance. Presently used SiO
2
has a relative dielectric constant of about 4, which limits its use because of potential cross-talk and RC delays.
Subsequent technologies will use dielectrics that have a lower dielectric constant than SiO
2
to reduce wiring capacitance and overall chip delay. In the past, integration of damascene structures into low dielectric constant materials has been difficult or nearly impossible due to the relatively poor film properties, e.g. hardness, adhesion, stability and stress, or the difficulty in the anisotropic etching of low dielectric constant dielectrics compared with SiO
2
.
In view of the problems associated with integrating low dielectric constant dielectrics into damascene structures, there remains a need for providing a simple, yet effective method of fabricating damascene structures which contain a dielectric material, i.e. insulator, that has a lower dielectric constant than SiO
2
. Such a method would eliminate the integration problems normally encountered in fabricating damascene wiring structures.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a damascene structure which contains a dielectric material having a dielectric constant lower than 4.0, i.e. the dielectric constant of SiO
2
.
Another object of the present invention is to provide a simple, yet effective method of fabricating a damascene structure containing a dielectric material having a dielectric constant lower than SiO
2
which eliminates the integration problems normally associated with prior art processes.
A further object of the present invention is to provide a method of fabricating a damascene structure which has little or no delay problems caused by cross-talk or stray capacitance.
These as well as other objects and advantages are achieved in the present invention by etchingback the intermetal dielectric of a damascene structure so as to expose the in-laid wiring of said structure. Specifically, the foregoing objects are met by the method of the present invention which comprises the steps of:
(a) etching an intermetal dielectric of a damascene structure having planarized in-laid wiring, wherein said etching is carried out between said in-laid wiring so as to expose said in-laid wiring in said intermetal dielectric;
(b) forming a dielectric material having a dielectric constant lower than SiO
2
and the intermetal dielectric on said structure provided in step (a); and
(c) planarizing the structure provided in step (b).
In an optional embodiment of the present invention, a polish stop layer is formed on the etchbacked structure provided in step (a) and thereafter steps (b) and (c) are performed. This optional embodiment is typically carried out when the low dielectric constant material is not compatible with the wiring material; or to act as a polish stop layer during the planarization step; or, if necessary, as a RIE stop during a subsequent via reactive ion etch (RIE) step.
In yet another optional embodiment of the present invention, a cap layer comprising a dielectric material such as SiO
2
or fluorinated SiO
2
is formed on the surface of the low dielectric constant material prior to planarizing the structure. This optional embodiment is typically employed when the low dielectric constant material is not compatible with the planarization step.
It is again noted that the above processing steps provide a dual or single damascene wiring structure. Dual damascene structures containing multiple wiring levels can also be obtained by providing a via and a metal line or alternatively a metal line and then a via to the planarized structure; filling with a metal and planarizing the line and via; and then repeating steps (a)-(c) above along with any of the above mentioned optional embodiments.
When a single damascene structure is desired, the method of the present invention is nearly identical to the method described above. It is noted that the single damascene embodiment may use a low dielectric constant dielectric for the wiring levels only and leave SiO
2
in the via level of the wiring levels or alternatively use a low dielectric constant dielectric for the via level only and leave SiO
2
in the wiring level. When a single damascene structure is desirable, it is also possible to use any of the optional embodiments described above.
In another aspect of the present invention, a damascene structure (both dual and single) containing a dielectric material having a dielectric constant lower than SiO
2
is provided. In accordance with this aspect of the present invention, the dual damascene structure comprises a planarized wiring structure having an upper and a lower wiring level, wherein said upper wiring level comprises an etchbacked intermetal dielectric, exposed in-laid wiring, an optional polish stop layer formed on said etched intermetal dielectric and said exposed in-laid wiring, a dielectric material having a dielectric constant lower than SiO
2
on said etchbacked structure or on said polish stop layer, and an optional cap layer on said low dielectric constant material. It is noted that the polish stop layer could also function as a diffusion barrier between the wiring and interlevel or intrametal dielectrics. In the case of the single damascene structure, an interconnect level is located between the wiring levels.
Damascene structures containing multiple wiring levels are also contemplated in the present invention. These damascene structures containing multiple wiring levels comprise alternating wiring levels and optional interconnect levels, between said wiring levels, wherein the intermetal dielectric of the various upper wiring levels are processed using steps (a)-(c) of the present invention.
It is noted that in the present invention, the initial dielectric material may be SiO
2
or it is also possible to use a material with a dielectric constant less than SiO
2
as the initial dielectric material. Likewise, this also applies to the optional cap layer which is deposited on top of the low dielectric constant dielectric. Thus, SiO
2
or alternatively a low dielectric constant dielectric which has a higher dielectric than the underlying low d
McGahay Vincent J.
Stamper Anthony K.
Goodwin David J
International Business Machines - Corporation
Scully Scott Murphy & Presser
Walter Howard J.
Wilczewski Mary
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