Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-20
2002-10-01
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C438S687000
Reexamination Certificate
active
06458650
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating the second electrode of a Metal-Insulation-Metal (MIM) capacitor while preventing corner spiking which typically results in leakage current.
(2) Description of the Prior Art
One of the materials that is used during the creation of semiconductor devices is silicon nitride. As an example, silicon nitride can be used as a layer of insulation between the first and the second electrode of a Metal Insulator Metal (MIM) capacitor, forming the capacitor dielectric of the MIM capacitor. A frequently used layer of insulation is a stacked layer of oxide-nitride-oxide (ONO) which is more precisely defined as a layer of silicon oxide over which a layer of silicon nitride over which a layer of silicon oxide is deposited. In the layer of oxide-nitride-oxide, the first layer of oxide is native oxide. The silicon nitride is grown in a low power furnace,,typically to a thickness within the range of between 40 and 60 Angstrom, after which the final layer of silicon oxide is grown. Layers of silicon nitride have however been recognized as being prone to the occurrence of molecular irregularities that occur at the interface of the silicon nitride layer with other surfaces. These molecular irregularities are most frequently classified as concentrations of negative charge carriers in the surface of the silicon nitride layer. These molecular irregularities cause an undesired interface between the layer of silicon nitride and an overlying layer and can result in leakage currents between the overlying layers or in an unsatisfactory threshold voltage barrier between the adjacent layers of which the layer of silicon nitride is one of the layers. Several approaches have been used to remove surface irregularities from the surface of a layer of silicon nitride. One of these methods applies a temperature bake to the surface. Anneals at elevated temperatures are frequently used in the semiconductor art with the objective of eliminating undesired molecular disturbances. Another approach is to remove a small layer of silicon nitride from the surface of the layer and to therewith remove the negative charge carriers in the surface of the silicon nitride layer. The high temperature anneal of the surface of the layer of silicon nitride is for a number of applications of limited value since this high temperature processing is likely to affect and disturb other interfaces and elements of a semiconductor device.
One of the more detrimental effects of exposing semiconductor surfaces to ambient air is that elements contained in the air affect the exposed surface, in many instances with undesirable results. It is for instance well known in the art that copper has the disadvantage of being readily oxidized at relatively low temperatures. The high susceptibility of copper to oxidation means that conventional photoresist processing cannot be used when the copper is to be patterned into various shapes, such as interconnect traces or damascene structures, because the photoresist needs to be removed at the end of the process by heating it in a highly oxidized environment, such as an oxygen plasma, thereby converting it to an easily removed ash.
As part of the creation of semiconductor devices, the creation of layers of oxide over a surface is frequently used in a controlled manner, such as for instance the creation of a layer of pad oxide for gate electrodes. The removal of concentrations of negative charge carriers in the surface of the silicon nitride layer may therefore also be considered possible by exposing the silicon nitride layer to air, causing oxidation of the surface of the layer of silicon nitride which can then be removed by various methods. This method however is without promise since silicon nitride does not oxidize.
The invention addresses the creation of a copper MIM capacitor, which uses silicon nitride as a layer of insulation for the dielectric. Conventional methods of creating an opening for the second electrode expose the surface of the dielectric over which the second electrode is then created. Conventional processes that are used for the creation of the opening for the second electrode cause surface irregularities (spiking in the surface) of the exposed layer of silicon nitride. These irregularities most typically occur in the surface interface between the layer of silicon nitride and the adjacent copper (corner spiking). The invention addresses this problem and provides a method where the surface of the layer of silicon nitride can be exposed without causing surface irregularities in the surface of the exposed layer of silicon nitride.
U.S. Pat. No. 5,434,109 (Geissler et al.) shows a process to oxidize silicon nitride.
U.S. Pat. No. 6,127,089 (Subramanian et al.), U.S. Pat. No. 6,072,227 (Yau et al.) and U.S. Pat. No. 6,153,514 (Wang et al.) show related dual damascene processes.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a method for creating a Metal Insulation Metal (MIM) capacitor of improved performance.
Another objective of the invention is to provide a method of creating a MIM. capacitor having an improved interface between the capacitor dielectric and the overlying second electrode of the capacitor.
Yet another objective of the invention is to provide a method of creating a MIM capacitor that has low leakage current between the first and the second electrode of the capacitor.
In accordance with the objectives of the invention a new method is provided for the creation of an opening over which the second electrode of a MIM capacitor is to be deposited. The first electrode of the MIM is created in a first layer of Fluorine doped Silicon dioxide (SiO
2
) Glass (FSG). A layer of insulation comprising silicon nitride is deposited over the surface of the first electrode. A second layer of Fluorine doped Silicon dioxide (SiO
2
) Glass (FSG) is deposited over the surface of the layer of silicon nitride, an etch stop layer of silicon nitride is deposited over the surface of the second layer of FSG. The layers of etch stop and the second layer of FSG are patterned and etched using a dry etch, stopping on the layer of insulation and exposing the surface of the layer of insulation. Next and of critical importance to the invention is a step of photoresist ashing and oxidation of the surface of the layer of silicon nitride. The layer of photoresist can now be removed while concurrently, using a wet strip, the layer of silicon nitride oxidation is removed from the surface of the layer of silicon nitride. The process of creating a MIM capacitor can then proceed by creating the second electrode of the MIM capacitor.
REFERENCES:
patent: 5434109 (1995-07-01), Geissler et al.
patent: 6072227 (2000-06-01), Yau et al.
patent: 6127089 (2000-10-01), Subramanian et al.
patent: 6143598 (2000-11-01), Martin et al.
patent: 6153514 (2000-11-01), Wang et al.
patent: 6303426 (2001-10-01), Alers
Chao Li-Chih
Chen Chao-Chen
Huang Yi-Chen
Ackerman Stephen B.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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