Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-02-15
2004-02-10
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S648000
Reexamination Certificate
active
06689684
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing semiconductor devices having dimensions in the deep sub-micron regime with greater reliability. The present invention has particular applicability in manufacturing high density, multi-level semiconductor devices comprising copper and/or copper dual damascene interconnection structures and exhibiting high circuit speed.
BACKGROUND ART
Interconnection technology is constantly challenged to satisfy the ever-increasing requirements for high density and performance associated with ultra large scale integration semiconductor devices. As the feature sizes continue to shrink it becomes increasingly difficult to form interconnection patterns exhibiting the requisite circuit speed with high dimensional accuracy and reliability.
The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the R×C product, the more limiting the circuit speed. As integrated circuits become complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the performance of multi-level interconnects is dominated by interconnect capacitance at deep sub-micron regimes, e.g., less than about 0.18 micron. The rejection rate due to integrated circuits speed delays in sub-micron regimes has become a limiting factor in fabrication.
The dielectric constant of materials currently employed in the manufacture of semiconductor devices for an interlayer dielectric (ILD) ranges from about 3.9 for dense silicon dioxide to over 8.0 for deposited silicon nitride. The value of the dielectric constant expressed herein is based upon a value of one for a vacuum. In an effort to reduce interconnect capacitance, dielectric materials with lower values of permitivity have been explored. The expression “low-k” material has evolved to characterize materials with a dielectric constant less than about 3.9, based upon a value of the dielectric constant of a vacuum as one (1). One type of low-k material that has been explored are a group of spin on or CVD siloxane materials, such as hydrogen silsesquioxane (HSQ) and methyl silsesquioxane (MSQ) and Black-Diamond™ dielectric available from Applied Materials, Santa Clara, Calif.,. There are several organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which offer promise for use as an ILD, such as FLARE 20™ dielectric, a poly(arylene) ether, available from Allied Signal, Advanced Micromechanic Materials, Sunnyvale, Calif. BCB (divinylsiloxane bis-benzocyclobutene) and Silk™ dielectric, an organic polymer similar to BCB, both available from Dow Chemical Co., Midland, Mich.
In implementing Cu and/or Cu alloy damascene techniques to form interconnection patterns with dimensions in the deep sub-micron regime, particularly when employing various low-k materials, including porous oxides, such as dielectric oxides having a porosity of about 30% to about 80% and a dielectric constant (k) of about 2.0 or lower, various problems evolve which degrade the resulting semiconductor device. For example, copper readily diffuses into conventional silicon-based materials such as polysilicon, single-crystalline, silicon dioxide, low-k inorganic and organic materials. Once semiconductive silicon-based materials are Cu doped, transistors made within or in close proximity to the Cu doped silicon-based regions either cease to function properly or are significantly degraded in electrical performance.
Accordingly, there exists a need for methodology enabling the manufacture of interconnection patterns having feature sizes in the deep sub-micron regime with greater dimensional accuracy, increased circuit speed, and improved reliability. There exists a particular need for methodology enabling the formation of semiconductor devices comprising Cu and/or Cu alloy interconnection patterns with improved reliability and increased circuit speed.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device exhibiting improved reliability and increased circuit speed.
Another advantage of the present invention is a semiconductor device comprising a Cu or a Cu alloy interconnection pattern exhibiting high circuit speed and improved reliability.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a copper (Cu) or Cu alloy feature in a first dielectric layer; forming a composite layer on an upper surface of the Cu or Cu alloy feature and on an upper surface of the first dielectric layer, the composite layer comprising: (a) a first capping layer portion, comprising a first material, formed at least on the upper surface of the first dielectric layer; and (b) a second barrier layer portion having first and second side surfaces adjoining the first capping layer portion, the second barrier layer portion comprising a second material different from the first material and on at least part of the upper surface of the Cu or Cu alloy feature; forming a second dielectric layer on the composite layer overlying the first dielectric layer; etching to form an opening defined by side surfaces and upper corners of the second dielectric layer and to expose an upper surface of the second barrier layer portion; and sputter etching to round the upper corners, to remove at least part of the exposed second barrier layer portion and to redeposit the removed part of the second barrier layer portion on the side surfaces of the second dielectric layer to form a first barrier layer sidewall thereon.
Another aspect of the present invention is a semiconductor device comprising: a lower copper (Cu) or Cu alloy feature in a first dielectric layer; a lower capping layer on at least an upper surface of the first dielectric layer; a second dielectric layer on the lower capping layer overlying the first dielectric layer; an opening defined by side surfaces of the second dielectric layer; a first barrier layer on the side surfaces of the second dielectric layer; and a second barrier layer sidewall on the first barrier layer sidewall with an interface therebetween.
Embodiments of the present invention include forming the capping layer from silicon nitride, silicon oxynitride or silicon carbide, and forming the barrier layer portion of the composite layer of Ta or TaN. Embodiments of the present invention further include forming the first barrier layer sidewall at a thickness of about 50 Å to about 11 Å. In accordance with embodiments of the present invention, the composite barrier/capping layer can be formed by depositing the capping layer, forming a photoresist mask thereon, and etching to remove all or a portion of the capping layer to form an opening or a recess, respectively, therein. The opening or recess is then filled with the barrier layer material and CMP conducted to planarize the upper surface. Embodiments of the present invention further include sputter etching to remove all or a portion of the exposed barrier layer to form the barrier layer sidewall.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embod
Huang Richard J.
Wang Fei
You Lu
Advanced Micro Devices , Inc.
Dang Phuc T.
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