Cross-coupled transistor memory cell for MOS random access memor

Details Cross-coupled transistor memory cell for MOS random access memor Cross-coupled transistor memory cell for MOS random access memor

1982-12-20

1985-03-19

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365154, 365190, 307449, G11C 1140

Patent

active

045063494

ABSTRACT:
A memory cell of the general type employing one pair of IGFETs defining data nodes and cross-coupled in a latch circuit configuration for storing data, and another pair of IGFETs serving as transmission gates to selectively couple data into or out of the cell. A circuit technique provides fast writing speed by avoiding the use of load resistors in either the charge or discharge paths for the data nodes and yet ensures that the data nodes are pulled either fully to logic high or fully to logic low, as the case may be, without limitation by threshold voltage offset between the gate and source terminals of the IGFETs serving as transmission gates. High impedance leakage current discharge resistances are included, and serve only the function of discharging leakage at the nodes to maintain memory. In the disposed circuit configurations, the latch IGFETs are of opposite channel conductivity type compared to the gating IGFETs. Various alternative forms of suitable high impedance leakage current resistances are disclosed, including a resistive sea above the cell and leakage paths included within the gating IGFETs. The high impedance leakage current discharge resistances may be eliminated to provide a dynamic memory cell.

REFERENCES:
patent: 3521242 (1970-07-01), Katz
patent: 3535699 (1970-10-01), Gaensslen et al.
patent: 3967252 (1976-06-01), Donnelly
patent: 4063225 (1977-12-01), Stewart
patent: 4189782 (1980-02-01), Dingwall
patent: 4251876 (1981-02-01), McKenny et al.
patent: 4335449 (1982-06-01), Nokubo
patent: 4459683 (1984-07-01), Yalamanchili et al.

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