Crackstop with release layer for crack control in...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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Details

C438S128000, C438S129000, C438S424000

Reexamination Certificate

active

07109093

ABSTRACT:
Methods of forming and the integrated circuit device structure formed having vertical interfaces adjacent an existing crack stop around a perimeter of a chip, whereby the vertical interface controls cracks generated during side processing of the device such as dicing, and in service from penetrating the crack stop. The vertical interface is comprised of a material that prevents cracks from damaging the crack stop by deflecting cracks away from penetrating the crack stop, or by absorbing the generated crack energies. Alternatively, the vertical interface may be a material that allows advancing cracks to lose enough energy such that they become incapable of penetrating the crack stop. The present vertical interfaces can be implemented in a number of ways such as, vertical spacers of release material, vertical trenches of release material or vertical channels of the release material.

REFERENCES:
patent: 6091131 (2000-07-01), Cook et al.
patent: 6174814 (2001-01-01), Cook et al.
patent: 6261945 (2001-07-01), Nye, III et al.
patent: 6492247 (2002-12-01), Guthrie et al.
patent: 2005/0026397 (2005-02-01), Daubenspeck et al.
patent: 2005/0269702 (2005-12-01), Otsuka

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