Counterbore dielectric plasma etch process particularly...

Details Counterbore dielectric plasma etch process particularly... Counterbore dielectric plasma etch process particularly...

1998-07-09

2001-04-03

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S723000, C438S724000, C438S725000, C438S736000

Reexamination Certificate

active

06211092

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to plasma etch processes. In particular, the invention relates to the highly selective etching of insulating materials, particularly silicon oxide, forming part of a complex integrated-circuit structure.
BACKGROUND ART
The technology of fabricating semiconductor integrated circuits continues to advance in the number of transistors, capacitors, or other electronic devices which can be fabricated on a single integrated circuit chip. This increasing level of integration is being accomplished in large part by decreasing the minimum feature sizes. Even as the number of layers in the integrated circuit continues to increase, advanced processes are being used which allow for a reduction in the number of processing steps for a functional layer. However, these advanced processes often make extraordinary demands upon the chemistry of the etching process. Dielectric etching has presented some of the most difficult demands.
In the past the common materials for inter-level dielectric have been based upon silicon, such as silicon dioxide, silica glass such as BPSG, and related silicon-based oxide materials that serve as electrical insulators. Recently, interest has developed in insulating materials with low dielectric constants (low-k dielectrics), some of which are based upon silicon but others are based upon carbon.
Advanced integrated circuits contain multiple wiring layers separated from the silicon substrate and from each other by respective dielectric layers. Particularly logic circuitry, such as microprocessors, require several layers of metallization with intervening inter-level dielectric layers. Small contact or via holes need to be etched through each of the dielectric layers. The contact or via holes are then filled with a conductor, composed typically of aluminum in the past but more recently composed of copper. A horizontal wiring layer is formed over one dielectric layer and then covered by another dielectric layer. The horizontal wiring and the underlying vias are often referred to as a single wiring layer. The conventional process not only fills the contact or via holes but also overfills them to form a thick planar layer over both the filled holes and the dielectric. Conventionally, a metal lithographic step then photographically defines a photoresist layer over the planar metal layer and etches the exposed metal into a network of conductive interconnects.
In contrast, a recently developed damascene process substitutes chemical mechanical polishing for metal etching. A dual-damascene structure, as illustrated in sectioned isometric view in
FIG. 1
, has been proposed for advanced chips which avoids the metal etching and combines the metallization of the via and horizontal interconnect. There are two general types of dual-damascene processes, self-aligned and counterbore. The more conventional self-aligned dual-damascene process will be described first.
Over a substrate
10
is formed a thin lower stop layer
12
having a minimal thick of, for example 100 nm, a lower dielectric layer
14
, having a thickness of, for example, 1 &mgr;m or somewhat less, and a thin upper stop layer
16
. The stop layers
12
,
16
have compositions relative to the dielectric material such that a carefully chosen etch process that is selective to the material of the stop layer etches through the overlying dielectric but stops on the stop layer. Although copper metallization and low-k dielectric would more fully utilize the advantage of the dual-damascene structure, the present description will use silicon dioxide as the principal inter-level dielectric. Silicon dioxide is preferably grown by plasma-enhanced chemical vapor deposition (PECVD) using tetraethylorthosilicate (TEOS) as the main precursor gas. Silicon nitride (Si
3
N
4
) is a common material for stop layers when the dielectric is an oxide. Silicon nitride is preferably also grown by PECVD to reduce the thermal budget, and its general composition is given by SiN
x
, where x may vary somewhat over a range of, for example 1 to 1.5. A dielectric photolithographic step is then performed to create circular holes
18
in the upper stop layer
16
. The diameters of the circular holes
18
determine the diameters of the via holes, which usually represent the smallest dimension defined in the dielectric etch. The smallest defined lateral dimension in a level is often referred to as the critical dimension (CD). The dual-damascene structure can be used both at the power level, which is the uppermost metal layer, and at the signal levels, for example, metal-
1
and metal-
2
levels for a moderately complex logic chip. The power level typically has a larger via size, for example, 0.6 &mgr;m, while the signal levels typically have smaller via sizes, for example, 0.3 &mgr;m. This diameter is being reduced to 0.25 &mgr;m and to yet lower sizes in advanced structures. Total dielectric thickness also varies between the power and signal levels. The etching in this photolithographic step is preferably selective to the principal dielectric material so that at this point the holes
18
do not significantly extend into the lower dielectric layer
14
.
Then, in the continuation of the self-aligned dual-damascene process, an upper dielectric layer
20
is deposited to a thickness of, for example, 1.4 &mgr;m over the partially etched structure, including deposition into the etched depressions in the patterned nitride layer
16
. A photoresist mask is deposited and defined into the shape of a trench
22
having a width of, for example, 1.2 &mgr;m and a much longer length. A self-aligned dual-damascene dielectric etch is then performed both to form the trench
22
in the upper oxide layer
20
and to extend the lower via holes
18
through the lower oxide layer
14
and down to the lower stop layer
12
. The upper nitride stop layer
16
serves both as a stop for forming the trench
22
and as a hard mask for etching the via hole
18
. The combined etch must not significantly etch the upper stop layer
16
at the floor
24
of the trench
22
, and it must stop at the lower stop layer
12
at the bottom
26
of the via holes
18
. In a further step, not illustrated here because it is generally considered to be non-crucial, a further non-selective etch removes the portion of the lower stop layer
12
at the bottom of the via hole
18
so as to expose the substrate
10
to contacting when metal is filled into the trench
22
and via hole
18
.
In the self-aligned dual-damascene etch process, the selectivity of the oxide etch to nitride or other stop material in both the relatively open trench floor
24
and particularly at the shoulders
28
of the via holes
18
is especially crucial since these areas are exposed to the etching plasma while the via holes
18
are being etched. Generally, the shoulders
28
etch faster than the trench floor
24
because of the exposed geometry. The upper nitride layer
16
and its shoulder
28
are further exposed during a long over-etch of the lower oxide layer
14
, typically greater than 100% to reliably open the via in the presence of process and other non-uniformities. Such selectivity can be achieved by use of a highly polymerizing chemistry which deposits a protective polymeric coating on the non-oxide surfaces and vertical oxide surfaces but generally not on the horizontal oxide surfaces. However, the extensive polymerization impacts the etching of the narrow and deep via holes
18
and may cause etch stop. Etch stop occurs when the side walls are so heavily polymerized that the polymer closes the hole and prevents further etching of the bottom of the hole. Of course, etch stop in the via holes
18
must be avoided. As a result, the process window for the self-aligned process is often limited by the conflicting requirements of the oxide etch to maintain the nitride shoulders
28
while continuing to open the oxide in the via hole
18
. The etch must maintain the bottom critical dimension (CD) associated with the via hole
18
in order to maintain tight control of the vi

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