Copper vias in low-k technology

Details Copper vias in low-k technology Copper vias in low-k technology

2001-01-11

2002-05-07

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S643000, C438S644000, C438S653000, C438S654000

Reexamination Certificate

active

06383929

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is that of forming integrated circuits with copper metallization and low-k dielectrics,
BACKGROUND OF THE INVENTION
In the field of copper with oxide, the art has developed a set of compatible materials to line the trenches and vias that contain the copper. The lining must adhere to the dielectric and block diffusion.
Conventionally, in oxide dielectric circuits, a dual damascene structure combining a via connected to a lower level with a horizontal interconnection member includes an adhesion layer of Ta or TaN, a barrier layer of TaN to prevent diffusion of the copper and a top layer of Ta or TaN prior to Cu seed deposition.
As the dimension of semiconductor devices continues to shrink, the RC delay of its metal interconnects becomes a major limiting factor of the device speed. In order to resolve this issue, implementation of copper interconnects (which reduces resistance, R) in a low-k dielectric material (which reduces capacitance, C, between the metal lines) becomes a key issue for the semiconductor industry to shrink the device deep sub-micrometer dimension.
The most economical way to implement Cu low-k metallization process is to use a dual-damascene structure with metal via and metal lines being etched and filled with Cu metal in one process step. The excess Cu is removed by CMP (chemical mechanical polishing). In a dual-damascene structure, a barrier layer (or multiple layers) between the Cu metal and the dielectric material is required for both metal vias and metal lines. This barrier layer is known as a liner. The liner has two functions: as a Cu diffusion barrier to prevent Cu from diffusing into the dielectric material and as a contact layer between Cu metal via and underlying metal line (which can be made of Cu or W).
In the field of Cu dual-damascene metallization structures in SiO
2
dielectric (which is not considered as low-k dielectric material), the prior art has developed a set of compatible materials for the liner, such as Ta, TaN, and CVD TiN. It has been discovered that Ta has good adhesion with Cu metal and CVD TiN has better coverage on the sidewall of the line and via, especially for high aspect ratio structures.
However, in the field of forming Cu metal interconnects in low-k dielectric material, new problems have arisen that do not have a counterpart in the Cu metal interconnects in SiO
2
dielectric. For instance, one of the low-k dielectric such as SILK has several material properties that do not exist in SiO
2
. SiLK is polymer material, and is largely made of C. SiLK is also a soft material with a very high thermal expansion coefficient. Because of these unique properties of SiLK material, the requirements for Cu metal interconnects in that material, such as coverage of the sidewall of via and adhesion between liner and underlying metal (Cu or W metal), is different from corresponding requirements in Cu metallization in SiO
2
dielectric material.
In addition, the fact that the dimensions of vias and metal lines are decreasing, with a corresponding increase in the aspect ratio of vias, adds additional requirements on the liner for a dual-damascene structure.
SUMMARY OF THE INVENTION
The invention relates to a combination of materials and structure for copper interconnect circuits using low-k dielectrics that provides the required adhesion between the bottom of a via and the lower copper interconnection member, together with adequately low resistance.
A feature of the invention is that the adhesion between the bottom of a via and the underlying interconnect is sufficient to withstand the stress caused by thermal cycling.
Another feature of the invention is that carbon contamination on the bottom of a via is reduced by the gettering action of a layer of Ti.
Yet another feature of the invention is the formation of a high-strength, relatively high resistance Ti-Cu alloy only in the small region at the base of the via, thereby limiting the amount of resistance in the interconnect.


REFERENCES:
patent: 6080669 (2000-06-01), Iacoponi et al.
patent: 6303490 (2001-10-01), Jeng
US Pre-Grant Publication US 2001/0033025 A1.

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