Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-05-15
2003-11-18
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S625000, C438S629000, C438S631000, C438S687000, C438S697000, C205S640000
Reexamination Certificate
active
06649513
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication and more specifically to methods of non-mechanical planarization of copper structures.
BACKGROUND OF THE INVENTION
Copper (Cu) damascene processing requires chemical mechanical polishing (CMP) to polish/remove copper on the field area and polish/planarize the copper in the trench, for example, to form a planarized interconnect. However the CMP process creates problem issues such as peeling, dishing and erosion for example.
An electropolish technique may be used to remove/planarize the copper without using mechanical force. However, the copper barrier layer must still be removed using chemical mechanical polishing or etching using a dry or wet etch process which introduces the above problem issues.
U.S. Pat. No. 6,121,152 to Adams et al. describes a copper electropolish planarization process.
U.S. Pat. No. 6,017,820 to Ting et al. describes a copper electropolishing tool.
U.S. Pat. No. 5,567,300 to Datta et al., U.S. Pat. No. 6,207,222 B1 to Chen et al. and U.S. Pat. No. 6,171,960 B1 to Lee describe related doped copper processes.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of forming non-mechanical planarized copper structures.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure is provided. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having an opening formed therein and exposing at least a portion of the structure. A first-metal layer is formed over the patterned dielectric layer filling the opening. The first-metal layer including at least a doped metal portion adjacent the patterned dielectric layer. The doped metal portion being doped with a second-metal. The structure is annealed to form a second-metal oxide layer adjacent the patterned dielectric layer. The first-metal layer and the second-metal oxide layer are planarized using only a electropolishing process to remove the excess of the first-metal layer and the second-metal oxide layer from over the patterned dielectric layer and leaving a planarized metal structure within the opening.
REFERENCES:
patent: 5567300 (1996-10-01), Datta et al.
patent: 6017820 (2000-01-01), Ting et al.
patent: 6066892 (2000-05-01), Ding et al.
patent: 6121152 (2000-09-01), Adams et al.
patent: 6171960 (2001-01-01), Lee
patent: 6207222 (2001-03-01), Chen et al.
patent: 6221758 (2001-04-01), Liu et al.
patent: 6395152 (2002-05-01), Wang
Chou Shih-Wei
Liang Mong-Song
Shue Winston
Tsai Ming-Hsing
Ackerman Stephen B.
Jr. Carl Whitehead
Pham Thanhha
Saile George O.
Stanton Stephen G.
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