Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-06-18
2002-05-14
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S629000, C438S660000, C438S675000, C438S678000, C438S680000
Reexamination Certificate
active
06387805
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to metal depositions in semiconductor integrated circuits. In particular, the invention relates to copper metallizations.
BACKGROUND ART
A critical part of any advanced semiconductor integrated circuit involves the one or more metallization levels used to contact and interconnect the active semiconductor areas, themselves usually residing in a fairly well defined crystalline silicon substrate. Although it is possible to interconnect a few transistors or other semiconductor devices, such as memory capacitors, within the semiconductor level, the increasingly complex topology of multiply connected devices soon necessitates another level of interconnect. Typically, an active silicon layer with transistors and capacitors formed therein is overlaid with a dielectric layer, for example, silicon dioxide. Contact holes are etched through the dielectric layer to particular contacting areas of the silicon devices. A metal is filled into the contact holes and is also deposited on top of the dielectric layer to form horizontal interconnects between the silicon contacts and other electrical points. Such a process is referred to as metallization.
A single level of metallization may suffice for simple integrated circuits of small capacity. However, dense memory chips and especially complex logic devices require additional levels of metallization since a single level does not provide the required level of interconnection between active areas. Additional metallization levels are achieved by depositing over the previous metallized horizontal interconnects another level of dielectric and repeating the process of etching holes, now called vias, through the dielectric, filling the vias and overlaying the added dielectric layer with a metal, and defining the metal above the added dielectric as an additional wiring layer. Very advanced logic device, for example, fifth-generation microprocessors, have five or more levels of metallization.
Conventionally, the metallized layers have been composed of aluminum or aluminum-based alloys additionally comprising at most a few percent of alloying elements such as copper and silicon. The metallization deposition has typically been accomplished by physical vapor deposition (PVD), also known as sputtering. A conventional PVD reactor
10
is illustrated schematically in cross section in
FIG. 1
, and the illustration is based upon the Endura PVD Reactor available from Applied Materials, Inc. of Santa Clara, Calif. The reactor
10
includes a vacuum chamber
12
sealed to a PVD target
14
composed of the material to be sputter deposited on a wafer
16
held on a heater pedestal
18
. A shield
20
held within the chamber protects the chamber wall
12
from the sputtered material and provides the anode grounding plane. A selectable DC power supply
22
biases the target negatively to about −600VDC with respect to the shield
20
. Conventionally, the pedestal
18
and hence the wafer
16
is left electrically floating.
A gas source
24
of sputtering working gas, typically chemically inactive argon, supplies the working gas to the chamber through a mass flow controller
26
. A vacuum system
28
maintains the chamber at a low pressure. Although the chamber can be pumped to a base pressure of about 10
−7
Torr or even lower, the pressure of the working gas is typically kept between about 1 and 1000 mTorr. A computer-based controller
30
controls the reactor including the DC power supply
22
and the mass flow controller
26
.
When the argon is admitted into the chamber, the DC voltage ignites the argon into a plasma, and the positively charged argon ions are attracted to the negatively charged target
14
. The ions strike the target
14
at a substantial energy and cause target atoms or atomic clusters to be sputtered from the target
14
. Some of the target particles strike the wafer
16
and are thereby deposited on it, thereby forming a film of the target material.
To provide efficient sputtering, a magnetron
32
is positioned in back of the target
14
. It has opposed magnets
34
,
36
creating a magnetic field within the chamber in the neighborhood of the magnets
34
,
36
. The magnetic field traps electrons, and for charge neutrality, the ion density also increases to form a high-density plasma region
38
within the chamber adjacent to the magnetron
32
. However, it is understood that a plasma of decreasing density extends towards the wafer
16
.
With the continuing miniaturization of integrated circuits, the demands upon the metallization have increased. Many now believe that aluminum metallization should be replaced by copper metallization. Murarka et al. provide a comprehensive review article on copper metallization in “Copper metallization for ULSI and beyond,”
Critical Reviews in Solid State and Materials Science
, vol. 10, no. 2, 1995, pp. 87-124. Copper offers a number of advantages. Its bulk resistivity is less than that of aluminum, 1.67 &mgr;&OHgr;-cm vs. 2.7 &mgr;&OHgr;-cm for pure material, and any reduction in resistivity offers significant advantages as the widths and thicknesses of the metallization interconnects continue to decrease. Furthermore, a continuing problem with aluminum metallization is the tendency of aluminum atoms in an aluminum interconnect carrying a high current density to migrate along the interconnect, especially away from hot spots, in a process called electromigration. Any excessive amount of such migration will break an aluminum interconnect and rendering inoperable the integrated circuit. Copper-based alloys exhibit significantly reduced levels of electromigration.
Copper metallization is an unproven technology and is acknowledged to offer difficulties not experienced with the conventional aluminum metallization. However, it may afford ways to circumvent problems inherent in aluminum metallization.
Murarka et al. in the aforecited review article recommend alloying copper with magnesium or aluminum to improve the interfacial qualities. Later work done by the Murarka group at Rensselaer Polytechnic Institute and their collaborators have developed a useful technique for forming dependable copper interconnects and provide a model for its operation. As Lanford et al. describe in “Low-temperature passivation of copper by doping with Al or Mg,”
Thin Solid Films
, vol. 262, 1995, pp. 234-241, sputtering is used, as illustrated in the schematic cross section of
FIG. 2
, to deposit a film of copper alloy on a substrate. The primary examples of the alloying element are aluminum and magnesium. The copper alloy film can be deposited as alternating layers of copper and the alloying element, or the two constituents can be co-sputtered, for example, by use of a copper alloy sputtering target. After completion of the sputtering at near to room temperature, the wafer is annealed, for example, at 400° C. in argon for 30 minutes. The annealing causes a large fraction of the magnesium to diffuse to the outside of a remaining copper film and to react with any oxygen present at the interfaces to form a film of magnesium oxide. The MgO film encapsulates the Mg-alloyed Cu body. The upper free surface of the copper film is passivated by the MgO film. Magnesium oxide is a stable oxide and stops growing at a thickness in the range of 5 to 7 nm. The thin oxide is not believed to cause a high contact resistance, but in any case the oxide can be removed by a sputter etch prior to the deposition of a subsequent metallization. Lanford et al., ibid., suggest that the free surface is oxidized to MgO by oxygen impurities in the argon.
Metallization in advanced integrated circuits faces a demanding requirement in filling high-aspect ratio holes. Increasing device density requires that the feature sizes be further reduced. However, dielectric breakdown has prevented the thickness of interlevel dielectric levels from being similarly reduced. As a result, the aspect ratio of vias and contacts has been increasing. The aspect ratio is the ratio of the depth of the hole through the dielect
Chiang Tony
Chin Barry
Ding Peijun
Hashim Imran
Sun Bingxi
Applied Materials Inc.
Guenzer Charles S.
Gurley Lynne A.
Niebling John F.
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