Convertible hot edge ring to improve low-K dielectric etch

Details Convertible hot edge ring to improve low-K dielectric etch Convertible hot edge ring to improve low-K dielectric etch

2000-02-11

2002-05-07

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

C438S690000, C438S716000, C438S719000, C438S734000, C438S745000

Reexamination Certificate

active

06383931

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices. More particularly, the present invention teaches a novel method for etching semiconductor devices incorporating low dielectric constant organic films, such as SiLK®, while maintaining one or more desirable feature attributes, including feature critical dimension.
2. Description of Related Art
Integrated circuits use dielectric layers, which have typically been formed from silicon dioxide, SiO
2
, to insulate conductive lines on various layers of a semiconductor structure. As semiconductor circuits become faster and more compact, operating frequencies increase and the distances between the conductive lines within the semiconductor device decrease. This introduces an increased level of coupling capacitance to the circuit, which has the drawback of slowing the operation of the semiconductor device. Therefore, it has become important to use dielectric layers that are capable of effectively insulating conductive lines against such increasing coupling capacitance levels.
In general, the coupling capacitance in an integrated circuit is directly proportional to the dielectric constant, K, of the material used to form the dielectric layers. As noted above, the dielectric layers in conventional integrated circuits have traditionally been formed of SiO
2
, which has a dielectric constant of about 4.0. As a consequence of the increasing line densities and operating frequencies in semiconductor devices, dielectric layers formed of SiO
2
may not effectively insulate the conductive lines to the extent required to avoid increased coupling capacitance levels.
In an effort to reduce the coupling capacitance levels in integrated circuits, the semiconductor industry has engaged in research to develop materials having a dielectric constant lower than that of SiO
2
, which materials are suitable for use in forming the dielectric layers in integrated circuits. To date, a number of promising materials, which are sometimes referred to as “low-K materials”, have been developed. Many of these new dielectrics are organic compounds.
Low-K materials include, but are specifically not limited to: benzocyclobutene or BCB; Flare™ manufactured by Allied Signal® of Morristown, N.J.; one or more of the Parylene dimers available from Union Carbide® Corporation, Danbury Conn.; polytetrafluoroethylene or PTFE; and SiLK®. One PTFE suitable for IC dielectric application is SPEEDFILM™, available from W. L. Gore & Associates, Inc, Newark, Del. SiLK®, available from the Dow® Chemical Company, Midland, Mich., is a silicon-free BCB.
SiLK® has a dielectric constant of 2.65, can be processed at temperatures up to 490° C., and is compatible with metals such as aluminum Al, copper Cu, and the barrier materials titanium Ti, and tantalum Ta. These properties make this material suitable for all existing complementary metal oxide semiconductor, or CMOS, interconnect technologies which implement aluminum lines and tungsten vias, as well as copper/damascene technologies.
During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. In these processes a photo resist material is deposited on the wafer and then is exposed to light filtered by a reticle. The reticle is generally a glass plate that is patterned with exemplary feature geometries that blocked light from propagating through the reticle.
After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials the exposed regions are removed, and in the case of negative photoresist materials the unexposed regions are removed. Thereafter the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material and thereby define the desired features in the wafer.
The development of an effective etching process for an organic low-K film such as SiLK® must take into account several criteria including etch rate, profile control, selectivity to underlying materials as well as hardmask and critical dimension (CD) control. The etching of low-K dielectric materials was at first approached as if a silicon-based dielectric were being etched. In the case of organic low-K films however, other chemistries and processes are often needed to effectively etch the material.
Etching may be accomplished in a dual-frequency capacitively-coupled, (DFC) dielectric etch system. One such is Lam Research™ model 4520 XLE™, available from Lam Research™ Corporation, Fremont Calif. A simplified view of this system is shown at FIG.
1
. Having reference to that figure, the system,
1
, operates with two different frequencies coupled to the top and bottom electrodes respectively,
5
and
7
. The frequencies used in this system are 27 MHz and 2 MHz, respectively, but alternate frequencies may also be implemented. The dual frequencies implemented in the system are provided by frequency drives
17
and
19
. This system provides total etching power of up to 3000 watts. This system utilizes rings, for instance
13
, at the wafer edge to keep the etching plasma confined. Processes are typically run at pressures of 100-300 mT, which are maintained within chamber
15
. The gap between the electrodes can be adjusted as required for the process, by means of a gap drive,
3
. Finally, the wafer is held for processing by means of an electrostatic chuck,
9
, formed in conjunction with the lower electrode
7
. Not shown in this diagram is the system for maintaining pressures within chamber
15
. Study of the principles hereinafter enumerated will render evident to those having skill in the art that these principals are applicable to a wide variety of semiconductor etching systems. Such systems incorporate a broad range of operating features and parameters, and the principles later detailed specifically contemplate their implementation in all such etching systems, within the range of operating parameters defined herein.
Low-K organic polymers, such as SiLK® can be etched via an oxidation (e.g. oxygen-based) or a reduction (e.g. hydrogen-based) chemical process. Because of the strong chemical nature of an oxygen-based etch an isotropic profile will result, unless a passivant such as a fluorocarbon or a hydrocarbon is added to protect the sidewalls during the etch. Although chemistries that use fluorocarbons as passivants give reasonable etch rates and profile control, the free fluorine from the fluorocarbon causes poor selectivity to the oxide hardmask. This particularly affects corner selectivity where the oxide hardmask is first exposed, and as a result CDs are degraded. At least two different oxygen-based chemistries have been utilized to etch low-K materials: N
2
/O
2
/H
2
and N
2
/O
2
/hydrocarbon, especially CH
4
and C
2
H
4
.
To facilitate discussion,
FIG. 2
illustrates a representative layer stack
100
during the etch process, including a photoresist layer
102
, a hard mask layer
104
, a low capacitance dielectric layer
106
and an etch stop layer
108
. Stack
100
is disposed on a substrate, for instance a wafer, not shown in this view. Etch stop layer
108
may represent, for example, an etch stop layer for a dual damascene process and is typically formed of a suitable etch stop material such as TiN, SiN, tetraethylorthosilicate or TEOS, or the like. Low capacitance dielectric layer
106
represents a layer of one of the organic low-K materials previously discussed.
Above low capacitance dielectric layer
106
there is shown disposed a hard mask layer
104
, which is typically formed of a material including but not limited to SiN, silicon oxynitride or SiON, and TEOS. Hard mask layer
104
represents the masking layer that is employed to etch the via/trench in low capacitance dielectric layer
106
. Each of the layers in the s

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