Contactless flash eprom using poly silicon isolation and process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438258, 438593, H01L 218247

Patent

active

059941863

ABSTRACT:
A contactless flash EPROM cell array with poly 1 isolation blocks and process for its manufacture. The cell array includes poly 1 isolation blocks that are spaced-apart from a pair of drain lines of adjacent cells along a poly 2 word line in a manner that isolates the pair of drain lines from an adjacent pair. The poly 1 isolation blocks are separated from a silicon substrate by an insulating layer and from overlying word lines by an interpoly insulator. This insulating layer also separates floating gates from the substrate. To make the cell array, an insulating-layer/poly 1/interpoly insulator stacked structure is first produced. The stacked structure is masked and patterned to define parallel, spaced-apart poly 1 strips and first and second poly 1 lines that are located between adjacent pairs of the poly 1 strips. Source and drain lines are then formed. Silicon dioxide is grown over the source and drain lines, followed by the formation of poly 2 word lines. Finally, a stacked etch is performed using the word lines as a self-aligned mask to pattern the first and second poly 1 lines to define first and second floating gates and to pattern the poly 1 strips to define poly 1 isolation blocks.

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