Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-06-21
2005-06-21
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S314000
Reexamination Certificate
active
06908818
ABSTRACT:
A contactless channel write/erase flash memory cell structure and its fabricating method for increasing the level of integration is disclosed. The present invention utilizes a buried diffusion method to form an N+-doped region that acts as a drain of the flash memory cell and a P-doped region underneath an oxide layer. The N+-doped region and the P-doped region extend to in a bit line direction and a metal contact is used to connect the two away from any of the N+-doped region and the P-doped region of the flash memory cell for decreasing the numbers of the metal contacts in the flash memory cell and reducing dimensions of the device.
REFERENCES:
patent: 5424567 (1995-06-01), Chen
patent: 5936887 (1999-08-01), Choi et al.
Hsu Ching-Hsiang
Yang Ching-Sung
Hsu Winston
Nelms David
Powerchip Semiconductor Corp.
Vu David
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