Configuration control in a programmable logic device using non-v

Details Configuration control in a programmable logic device using non-v Configuration control in a programmable logic device using non-v

1998-04-21

1999-10-19

Moise, Emmanuel L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714725, 326 39, 39580037, G01R 3128

Patent

active

059681969

ABSTRACT:
A boundary scan test circuit (JTAG) interface is used to provide data for a set of configuration latches within a Configuration Register. The Configuration Register is included within the JTAG structure as a Test Data Register (TDR). Each configuration bit within the Configuration Register consists of a Configuration Latch, and each configuration latch has an output used as a configuration control signal within an output logic macrocell. The configuration register's input signal is selectably provided from either a set of serially connected configuration bit non-volatile element sense latches or from the JTAG Test Data In (TDI) data pin for reconfiguration, prototyping, and testing.

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