4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Memory testing

Prashant Dubey

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Area efficient memory architecture with decoder self test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Built-in self-repairable memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Configurable memory architecture with built-in testing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Digital clock generator circuit with built-in frequency and...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
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Integrated scannable interface for testing memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Profile ID: LFUS-PAI-P-2272673

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