Conducting line of semiconductor device and manufacturing...

Details Conducting line of semiconductor device and manufacturing... Conducting line of semiconductor device and manufacturing...

2001-02-28

2002-10-15

Potter, Roy (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S706000

Reexamination Certificate

active

06465346

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a conducting line of a semiconductor device, and a method of manufacturing the conducting line using an aluminum oxide layer as a hard mask.
2. Description of the Related Art
As the integration density of semiconductor devices increases, the width of wires and the gap between the wires decreases. Accordingly, when a contact hole is formed between parallel spaced wires, the processing margin (e.g., an alignment margin during photolithography), decreases, thereby increasing the likelihood of a defective contact.
In an effort to improve the alignment margin, a self-aligned contact forming method has been utilized. However, even with the self-aligned contact method, as the integration density of semiconductor devices increases and the size of the pattern decreases, the misalignment margin limitations for photolithography are reached.
When forming such a self-aligned contact, a conductive layer, for example, a pad filled with polysilicon, is formed on an active region, and then a contact is formed on the pad. Even when a process of forming such a pad is used, an additional chemical mechanical polishing process for isolation of nodes is required. Due to the chemical mechanical polishing, and an etching process margin for forming a self-aligned contact, it is necessary to form a silicon nitride layer as a hard mask on a gate electrode and on a bit line electrode.
FIGS. 1 through 3
are cross-sectional views illustrating the conventional steps of forming a gate pattern. A gate oxide layer (not shown) is formed on a semiconductor substrate
10
such as a silicon substrate. Next, a conductive layer
12
and a capping insulation layer
14
are sequentially formed on the gate oxide layer, and a photoresist pattern
16
is formed for defining a gate line. The capping insulation layer
14
is formed of silicon nitride. Subsequently, the capping insulation layer
14
is patterned using the photoresist pattern
16
as a mask, and the photoresist pattern
16
is removed. Next, the conductive layer
12
is patterned using the capping insulation layer pattern
14
a
as a mask, thereby forming gate patterns
15
in parallel which are spaced a predetermined distance from each other on a predetermined region of the gate oxide layer. Each of the gate patterns
15
has a structure in which a conductive layer pattern
12
a
and a capping insulation layer pattern
14
a
are sequentially stacked. The conductive layer pattern
12
a
serves as a gate electrode.
Although not shown, in subsequent process steps, a silicon nitride layer is formed on the entire surface of the resultant structure having the gate patterns
15
, and spacers are formed on the sidewalls of the gate patterns
15
by anisotropically etching the silicon nitride layer. An interlayer insulation layer, for example, a high density plasma chemical vapor deposition (CVD) oxide layer, having an excellent characteristic of filling a gap, is formed on the resultant structure. Subsequently, the interlayer insulation layer is planarized using a chemical mechanical polishing process. The planarized interlayer insulation layer is patterned and etched to form a self-aligned contact exposing the semiconductor substrate
10
between the gate patterns
15
. A conductive layer is deposited on the entire surface of the resultant structure, and a chemical mechanical polishing process for node isolation is performed, thereby forming a self-aligned contact pad.
Note that with this conventional process, a capping insulation layer (a silicon nitride layer) having a thickness of about 2000 Å or more is necessary. This is because the capping insulation layer (silicon nitride layer) is etched during an etching process for forming the conducting line and the self-aligned contact. Also, one must take into account the “dishing” phenomena which occurs during the chemical mechanical polishing process required for node isolation. However, since the photoresist selectivity decreases as the size of a pattern decreases (e.g., a bar critical dimension), a thick silicon nitride layer (a capping insulation layer) becomes a significant burden when etching a conducting line such as a gate line or a bit line. This is described below in greater detail.
FIG. 4
is a graph illustrating the maximum thickness of a silicon nitride layer (a capping insulation layer) with respect to a bar critical dimension and the thickness of a photoresist pattern. Here, the dotted line indicates the critical thickness of photoresist which does not collapse with respect to bar critical dimensions.
Referring to
FIG. 4
, as the integration density of semiconductor devices increases, a bar critical dimension (“a” of
FIG. 1
) decreases. As shown in the graph, the height (thickness) of a photoresist pattern has a limit—the maximum aspect ratio b/a as shown in
FIG. 1
of the photoresist pattern is about 3.5—due to the collapse of the photoresist pattern. A decrease in the bar critical dimension decreases the photoresist selectivity during an etching process of a silicon nitride layer (a capping insulation layer), thereby restricting the available maximum thickness of the silicon nitride layer. For example, when a bar critical dimension is 150 nm and the thickness of a photoresist pattern is 3500 Å, the available maximum thickness of a silicon nitride layer is about 3.3×10
3
Å. However, when a bar critical dimension is 100 nm and the thickness of a photoresist pattern is 3500 Å, the available maximum thickness of a silicon nitride layer is about 2.7×10
3
Å.
FIG. 5
is a graph illustrating the thickness of a silicon nitride layer (a capping insulation layer) remaining after a conducting line is etched to a maximum thickness of the silicon nitride layer calculated in
FIG. 4
, that is, before a chemical mechanical polishing is performed. As shown in
FIG. 5
, the thickness of a remaining silicon nitride layer is limited at a certain bar critical dimension, and particularly, that node isolation margin decreases to zero as the bar critical dimension decreases. Here, the dotted line indicates the critical thickness of photoresist which does not collapse with respect to bar critical dimensions.
As described above, a decrease in the bar critical dimension decreases the photoresist selectivity during an etching process of a silicon nitride layer (a capping insulation layer), thereby restricting the available maximum thickness of the silicon nitride layer. This limits the thickness of the silicon nitride layer remaining after an etching process is performed to form a conducting line and a self-aligned contact. Accordingly, the silicon nitride layer is removed in a chemical mechanical polishing step for node isolation, so that the silicon nitride layer may not fulfill its function as a hard mask. In the worst case, an electrical short of a gate electrode or a bit line electrode may occur.
To overcome these problems, it is necessary to form a relatively thick silicon nitride layer (a capping insulation layer). However, as the bar critical dimension decreases, a photoresist selectivity decreases, so the thickness of the silicon nitride layer is restricted. In addition, the thickness of a photoresist pattern is restricted due to the collapse of the photoresist pattern. Accordingly, a thick silicon nitride layer (a capping insulation layer) is a significant burden in etching the silicon nitride layer.
SUMMARY OF THE INVENTION
To solve the above problems, it is a first object of the present invention to provide a conducting line of a semiconductor device, including an aluminum oxide layer to compensate for the photoresist selectivity decreasing as the bar critical dimension decreases.
It is a second object of the present invention to provide a method of forming a conducting line of a semiconductor device using an aluminum oxide layer as a hard mask, having a large selectivity with respect to a silicon ni

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