Electrical computers and digital processing systems: support – Computer power control – Power conservation
Patent
1996-12-09
2000-07-11
Sheikh, Ayaz R.
Electrical computers and digital processing systems: support
Computer power control
Power conservation
713322, 713330, G06F 132
Patent
active
060888075
ABSTRACT:
A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) stops the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.
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Bluhm Mark
Garibay, Jr. Raul A.
Herubin Margaret R.
Maher Robert
National Semiconductor Corporation
Sheikh Ayaz R.
Viger Andrew S.
Wiley David A.
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