Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-11-29
2004-07-20
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
06766488
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to digital data compression using content addressable memory devices.
BACKGROUND ART
During the last 15 years, emulation devices used to debug microcontroller code have gained in popularity. The emulator, as the test instrument, gives the user ability to see what is going on inside the microcontroller silicon. Quite often, the emulator has a special emulation chip, called a “bond-out”, that is performing the normal tasks of the real microcontroller while also bringing out the internal signals from the silicon so they can aid in the debugging by giving visibility to internal buses.
Lately, the demand for lower cost of the emulation chip as well as of the emulator has resulted in a need for solutions where the actual real customer silicon is used for the emulation. This leads to a struggle between silicon cost and emulation features, which results in very few pins carrying as much information as possible.
Currently, two different schemes are used. In a first scheme, only some of the information is transmitted as “packages” out of the silicon on a few pins. This may require the silicon to actually stall execution not to lose information. In a second scheme, selected parts of the information, such as every fourth program counter, are transmitted out, resulting in ambiguity due to the face that the program counter values that are in between never come out.
The object of the invention is to provide real-time, no-loss transmittal of user-selected information to be transferred over vew few IC pins with no limit to the input data which should be studied inside the silicon.
SUMMARY OF THE INVENTION
This invention brings out internal signals from a silicon device under test such as a microcontroller at real-time using a content addressable memory delivering an output bit pattern to as few IC pins as possible, a requirement for the modern microcontroller debug industry. The invention applies to so-called “soft cores” which typically are implemented in FPGA's and CPLD's, ASIC designs, as well as real microcontroller architectures.
The invention relies upon the occurrence of characteristic bit patterns to be generated repeatedly in data communications between a device under test and a tester. This allows a large number of bits of the characteristic bit pattern to be compressed by using a content addressable memory, CAM hereafter, to translate a large bit pattern to a small bit pattern, say as few bits as five, i.e. a token, while still allowing the emulation user to see and understand what is going on inside the device under test.
REFERENCES:
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patent: 6121905 (2000-09-01), Redford
patent: 6141743 (2000-10-01), Strongin
patent: 6185522 (2001-02-01), Bakker
patent: 6345372 (2002-02-01), Dieckmann et al.
patent: 6553453 (2003-04-01), Gibson et al.
Nohau Corporation
Schneck Thomas
Ton David
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