Complementary differential input buffer for a semiconductor...

Details Complementary differential input buffer for a semiconductor... Complementary differential input buffer for a semiconductor...

2000-03-09

2001-12-04

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230080, C326S080000, C326S083000

Reexamination Certificate

active

06327190

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an input buffer for a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices commonly include input buffers for converting the voltage level of a signal input from an external circuit to a voltage level suitable for an internal circuit. The input buffer operates to correctly detect the voltage level of the external signal to allow the semiconductor memory device to operate within normal parameters.
FIG. 1
is a circuit diagram of an N-type input buffer
101
of a conventional semiconductor memory device. Referring to
FIG. 1
, a conventional N-type semiconductor memory device
101
includes an NMOS transistor
111
for receiving external data IN, an NMOS transistor
112
for receiving a reference voltage Vref, a current mirror
131
constituted of PMOS transistors
121
and
122
, a PMOS transistor
123
for providing a supply voltage Vdd to the current mirror
131
in response to an external control signal PBPUB, and an inverter
141
for inverting data from a node N
1
and for outputting output data OUT of the N-type input buffer
101
.
In the case where the external input data IN is logic high in the N-type input buffer
101
, assuming that there is noise present in a ground voltage Vss, it takes longer for the data output from the node N
1
to transition from logic high to logic low due to the noise. Therefore, the length of time, or “skew”, for the data output from the node N
1
to transition from logic high to logic low, i.e. “high-voltage skew”, becomes larger. Accordingly, the set-up time and hold time margins of the data OUT output of the N-type input buffer
101
are reduced.
FIG. 2
is a circuit diagram of a P-type input buffer of a conventional semiconductor memory device. Referring to
FIG. 2
, a conventional P-type input buffer
201
includes a PMOS transistor
211
for receiving external data, a PMOS transistor
212
for receiving a reference voltage, a current mirror
231
constituted of NMOS transistors
221
and
222
, a PMOS transistor
213
for providing a supply voltage Vdd to the PMOS transistors
211
and
212
in response to the external control signal PBPUB, and an inverter
241
for inverting data from a node N
2
and for outputting the output data OUT of the P-type input buffer
201
.
In the case where the external data IN is logic low in the P-type input buffer
201
, assuming the presence of noise in the supply voltage Vdd, it takes longer for the data output from the node N
2
to transition from logic low to logic high due to the noise. Therefore, the skew time for the data output from the node N
2
to transition from logic low to logic high, i.e. “low-voltage skew”, becomes larger. Accordingly, the set-up time and hold time margins of the data OUT output of the P-type input buffer
201
are reduced.
As mentioned above, according to the conventional technology, since the high-voltage skew or low-voltage skew of the data OUT output from the input buffers
101
and
201
is relatively larger, the set-up time and hold time margins of the data OUT are reduced. Furthermore, it is increasingly difficult to reduce the skew of the data OUT as the trend toward ever-lower supply voltages Vdd continues.
SUMMARY OF THE INVENTION
To address the above-mentioned limitations, it is an object of the present invention to provide an input buffer for a semiconductor memory device by which it is possible to reduce the skew of output data.
It is another object of the present invention to provide an input buffer for a semiconductor memory device by which it is possible to reduce the skew of output data in a configuration that is amenable to use with semiconductor circuits of ever-lowering supply voltages.
Accordingly, to achieve the above objects, there is provided an input buffer for a semiconductor memory device. The input buffer includes a first differential amplifying portion including a first MOS transistor for receiving a first external input signal and a second MOS transistor for receiving a second external input signal. The voltage difference between the first and second external input signals is amplified and output as a first intermediate output voltage. A second differential amplifying portion includes a third MOS transistor for receiving the first external input signal and a fourth MOS transistor for receiving the second external input signal. The voltage difference between the first and second external input signals are amplified and output as a second intermediate output voltage. The first intermediate output of the first amplifying portion is combined with the second intermediate output of the second amplifying portion and the combined result is output as an output signal.
In a preferred embodiment, the first and second MOS transistors comprise NMOS transistors and the third and fourth MOS transistors comprise PMOS transistors.
The first differential amplifying portion preferably further comprises a first current mirror activated by the output of the second MOS transistor, for providing a supply voltage to the first and second MOS transistors. The first current mirror is preferably comprised of a plurality of PMOS transistors.
The second differential amplifying portion preferably further comprises a second current mirror activated by the output of the fourth MOS transistor, for providing a ground voltage to the third and fourth MOS transistors. The second current mirror is preferably comprised of a plurality of NMOS transistors.
Either the first external signal or the second external signal may comprise a reference voltage.
The input buffer of the present invention is less susceptible to fluctuations in ground and supply voltage levels due to noise, and the set-up time and hold time margins of the output signal are improved.


REFERENCES:
patent: 5670910 (1997-09-01), Kato
patent: 5723986 (1998-03-01), Nakashiro et al.
patent: 5793680 (1998-08-01), Okajima
patent: 5903508 (1999-05-01), Choi
patent: 5963053 (1999-10-01), Manohar et al.
Chappell, Terry, I., “A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAM,” IEEE International Solid-State Circuits Conference, ISSCC91 Technical Digest Session 3, 1999, pp. 50-51.

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