Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-23
2003-12-30
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06671840
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a communication system for controlling terminal units through boundary scan elements, and particularly to a communication system capable of coping with breakage of communication lines.
BACKGROUND OF THE INVENTION
A boundary scan test method has been proposed as one of the inspection methods, with a plurality of IC chips arranged over a printed wire board with printed wiring formed thereon, to see whether or not connection between each IC chip and each printed wiring is properly made and whether or not each printed wiring is broken.
This boundary scan test method can be applied to integrated circuits (IC chips) into which boundary scan elements are incorporated. The boundary scan element, for example as shown in
FIG. 4
, includes a plurality of boundary cells
214
individually provided between input/output terminals of an internal logic circuit
211
for implementing the inherent functions of the integrated circuit
210
and input terminals
212
and output terminals
213
of the integrated circuit
210
, a TAP controller (TAP circuits)
219
for controlling input and output of data to or from the boundary cells
214
, a TDI terminal
220
for receiving test data, a TDO terminal for transmitting test data, a TCK terminal
222
into which a clock signal is input, and a TMS terminal
223
for receiving a mode signal for switching the operation mode of the TAP controller
219
, and, if required, is further provided with a bypass register
215
, an ID CODE register
216
, an instruction register
217
, a TRS terminal
224
for receiving a reset signal, or the like. The bypass register
215
is to transfer communication data without being passed through the boundary cells, the ID CODE register
216
outputs an individually-assigned ID CODE to identify the source of the communication data, and the instruction register
217
decodes specific data among the communication data to carry out the transition or the like of the operation mode independent of a TMS signal. In this connection, the bypass register
215
to instruction register
217
are referred to as boundary scan register (
218
).
To describe the respective terminals or the signals to be input/output through the respective terminals in detail, TDI (Test Data In) is a signal for serial-inputting instructions and data to a test logic, and is sampled at rising edges of TCK. TDO (Test Data Out) is a signal for serial-outputting data from the test logic, the output value being changed at falling edges of TCK. TCK (Test Clock) supplies a clock to the test logic. It is a dedicated input for enabling the use of a serial test data path independent of the system clock inherent to the component. TMS (Test Mode Select) is a signal for controlling the test operation, and is sampled at rising edges of TCK. The TAP controller decodes this signal. TRST (Test Reset) is a negative logic symbol for asynchronously initializing the TAP controller, and is optional.
The integrated circuit
210
into which such boundary scan element is incorporated can run a test on the operating state thereof and the connecting relationship between this integrated circuit
210
and external devices, by the procedures described below.
First, in checking the quality of the internal logic
211
of the integrated circuit
210
, serial data (test data) are input to the TDI terminal
220
of the integrated circuit
210
as they are shifted, and thereby the test data are set into respective boundary cells
214
corresponding to respective input terminals
212
. In this state, the integrated circuit
210
is operated before the data set in the respective boundary cells
214
corresponding to respective output terminals
213
are shifted for output from the TDO terminal
221
, and, on the basis of the corresponding relationship between the serial data (test result data) thus obtained and the test data input to this integrated circuit
210
, the internal logic
211
of the integrated circuit
210
is tested for its quality.
The boundary scan test method can also be carried out on a plurality of integrated circuits as long as the boundary scan elements are incorporated therein.
For example, a plurality of integrated circuits
210
mounted on a substrate
226
as shown in
FIG. 5
can also be subjected to a test for breakage and the like of the printed patterns between the integrated circuits
210
, along with a test on the integrated circuits
210
themselves.
In this case, the respective boundary scan elements incorporated in the plurality of integrated circuits
210
are connected in series with-each other. Specifically, the TDO terminal
221
of the first integrated circuit
210
(the left in the drawing) and the TDI terminal
220
of the second integrated circuit
210
(the right in the drawing) are connected with each other, the output terminal
229
of a boundary scan controller board
228
provided in host computer unit
227
or the like and the TDI terminal
220
of the first integrated circuit
210
are connected with each other, and the input terminal
230
of the boundary scan controller board
228
and the TDO terminal
221
of the second integrated circuit
210
are connected with each other. The test procedures are as follows:
In testing breakage, short circuit, and the like of the printed patterns, a test data preparing tool
231
or the like is used to prepare test data (serial data), which is output from the output terminal
229
of the boundary scan controller board
228
and is input to the TDI terminal
220
of the first integrated circuit
210
while shifted, setting the test data into the respective boundary cells
214
corresponding to the respective output terminals
213
in this integrated circuit
210
. In this state, the data stored in these respective boundary cells
214
are output from the respective output terminals
213
provided in the first integrated circuit
210
as shown in
FIG. 6
, and are input through the respective printed patterns
233
constituting a system bus and the like to the respective input terminals
212
of the second integrated circuit
210
, and further captured into the respective boundary cells
214
corresponding to these respective input terminals
212
.
Thereafter, the data stored in the respective boundary cells
214
of these respective integrated circuits
210
are shifted and captured through the input terminal
230
of the boundary scan controller board
228
as they are analyzed by using a test result analyzing tool
232
or the like, so that a test can be made for breakage, short circuit, and the like in such a test range
235
as the printed patterns
233
providing connection between the integrated circuits
210
.
Next, in inspecting the internal logic
211
of the respective integrated circuits
210
, test data are output from the output terminal
229
of the boundary scan controller board
228
, and are input to the TDI terminal
220
of the first integrated circuit
210
as they are shifted, so as to be set into the respective boundary cells
214
corresponding to the respective input terminals
212
of this integrated circuit
210
as shown in FIG.
6
.
Subsequently, this integrated circuit
210
is operated, and the resulting data are captured into the respective boundary cells
214
corresponding to the respective output terminals
213
before the data stored in these respective boundary cells
214
are shifted for output from the TDO terminal
221
of the first integrated circuit
210
. Here, the second integrated circuit
210
is brought into a bypass state as shown in
FIG. 7
by the boundary scan controller board
228
, so that the data output from the TDO terminal
221
are bypassed through the second integrated circuit
210
and captured through the input terminal
230
of the boundary scan controller board
228
. Then, the test analyzing tools
232
or the like can be used for analysis of the captured data to test whether or not the first integrated circuit
210
operates properly.
Next, in the cases of inspecting the second integrated circuit
Abraham Esaw
Kanesaka & Takeuchi
Nagya Mitsugu
Ton David
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