Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2001-02-09
2003-03-18
Nguyen, Ha Tran (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S751000, C257S761000, C257S762000, C257S766000, C257S769000, C257S781000, C257S784000
Reexamination Certificate
active
06534863
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor processing, and more particularly to a process for fabricating a common ball-limiting metallurgy for input/output (I/O) sites used in packaging integrated circuit (IC) chips.
BACKGROUND OF TEE INVENTION
In the fabrication of semiconductor devices, metal lines are often embedded in dielectric layers in a multilevel structure, particularly in the latter stage (“back end of the line” or “BEOL”) of the fabrication process. The final layer containing metal lines (sometimes referred to in the art as the terminal via or TV layer) will have metal pads fabricated in contact with the metal lines, in a process sometimes referred to as “far back end of the line”, or “far BEOL”. The pads and lines together provide interconnects from the chip to other system components. The majority of IC chips use aluminum (Al) to form the interconnects, but more recently copper (Cu) is used.
Some advantages of using Cu rather than Al to form interconnects include higher conductivity (with lower resistance), lower capacitive load, lower power consumption, less crosstalk, fewer metal layers and fewer potential manufacturing steps. However, the disadvantages of using Cu include increased difficulty of depositing thin layers of Cu, potential for contamination of the Cu by underlying silicon thereby lowering performance, migration of Cu between lines, thereby increasing the risk of electrical shorts, and a mismatch in thermal expansion between the substrate and the Cu pads and lines. In order to take full advantage of Cu interconnects, methods of forming Cu interconnects must attempt to overcome these disadvantages of using copper.
Depending on the application, a variety of techniques are used to provide connections between a chip and other components, such as another level of interconnect. Common connections include wire bond and solder bumps.
Wire bonding is well-known in the art and used in the majority of IC chips, but disadvantages include a limited density of interconnect sites and, particularly during chip functional testing, there is the possibility of mechanical damage to the chip at the site of the bond. A typical example of a wire bond is illustrated in FIG.
1
B. In this prior art example, a substrate
120
has a metal line
115
embedded. The metal line could be aluminum or copper. A metal pad
114
, often composed of aluminum (Al) is formed over the metal line
115
, supported by a dielectric
110
. Typically, the aluminum pad will have an oxide layer
112
which forms readily over the surface because of the reactivity of aluminum. A wire
118
, often gold (Au), will be bonded to the pad using techniques known in the art, such as thermosonic bonding. One problem in forming wire bonds between gold and aluminum is that gold forms intermetallics with aluminum that can reduce the reliability of the bond.
Another problem with current integrated circuits, particularly those using Cu metallization, is that the low-k dielectrics employed are soft and sensitive to damage by pressure. Circuit testing is performed by pushing a set of test probes against critical conductive points on the top layer. The surface oxide must be broken through (often by a technique known as “scrubbing”) in order to form a good contact between the test probe and the pad metal. Therefore, particularly in the case of soft low-k dielectrics, the chip is subjected to potential mechanical damage. It would therefore be desirable to form an I/O pad that does not require scrubbing to provide low contact resistance with test probes.
Solder bump technology (known as flip chip technology in the art) potentially provides higher density and higher performance, but suffers from greater difficulty compared to wire bonding for rework and testing. An example of solder bump technology is controlled-collapse chip connection (C4) in which solder bumps are provided on both the chip and the interconnection substrate, and the connection is made by aligning the solder bumps of the chip and substrate and reflowing the solder to make the connections. The solder bumps are formed by depositing solder on a ball-limiting metallurgy (BLM) as illustrated in
FIG. 1A. A
metal feature
15
, which could be aluminum or copper, is formed in a substrate
16
. To prevent the solder from diffusing into the metal feature
15
, a multi-layer film of metal
10
is formed as a cap over the metal feature, and then the solder is formed onto the top of the multi-layer cap
10
which may initially extend beyond the cap onto the oxide surface. The ball-limiting metallurgy
10
is formed using multiple layers of metals, such as layer
11
including chromium, layer
12
including copper, and layer
13
including gold. The solder ball
18
is formed by initially depositing solder (a typical solder is 95% lead and 5% tin), using a process such as evaporation through a mask, which overlays the pad and a portion of the surface of the substrate
16
. The solder used for attaching flip chips to interconnection substrates has a relatively high melting point so that when the module containing the flip chip is assembled in subsequent packaging, other lower-melting point solders may be flowed without remelting of the flip chip solder connections. The ball
18
is then formed by heating the solder, which reflows into a ball, limited by the dimension of the BLM because of surface tension.
In view of the foregoing discussion, there is a need to provide an I/O site that can take advantage of copper metallization without degrading performance, reduce process steps and increase flexibility in preparing I/O sites.
SUMMARY OF THE INVENTION
The present invention addresses the above-described need by providing a process for fabricating a ball-limiting metallurgy (BLM) that can be used as a common site for both wire bond and controlled-collapse chip connection (C4) wafers.
This invention solves the problem of contamination of the metal lines by providing a diffusion barrier layer between the line and the I/O pad, and by providing a first recessed layer of metal within a feature formed in within a substrate upon which the I/O site of the present invention is formed.
This invention also solves the problem of damage to the chip caused by the forces of probing and/or wire bonding by providing a top layer of noble metal on the I/O site, which eliminates the presence of an oxide layer and requires less bonding force, and, in the case of gold wire bonding, no intermetallics are formed.
This invention has the advantage of reducing the number of process steps used to form an I/O site, and provides a flexible site that can be a common site for either a wire bond or a BLM, thereby reducing overall processing costs.
In accordance with one aspect of the invention, an input-output structure in a feature formed in a substrate, the substrate having a top surface, the feature having feature sidewalls and a feature bottom, the feature bottom formed over an electrically conductive material, the structure comprising:
a barrier layer covering the feature sidewalls and feature bottom, the barrier layer having a barrier bottom and barrier sidewalls;
a seed layer of metal having a seed bottom and seed sidewalls covering at least said barrier bottom; and
a first metal layer covering at least said seed bottom and having a recess formed therein, so that a top surface of said first metal layer is lower than the top surface of the substrate; and
a second metal layer covering said first metal layer.
In accordance with another aspect of the present invention, an input-output site is formed in a feature in a substrate, the substrate having a top surface, the feature having feature sidewalls and a feature bottom, the feature bottom formed over an electrically conductive material, the method comprising the steps of:
depositing a barrier layer covering the top surface of the substrate, the feature sidewalls and the feature bottom, so that the barrier layer has a barrier bottom and barrier sidewalls;
depositing a seed layer of metal covering the surface of said barr
Cheng Tien-Jen
Goldblatt Ronald D.
Gruber Peter A.
Horton Raymond R.
Petrarca Kevin S.
C. Li Todd M.
Nguyen Ha Tran
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