Combined resist strip and barrier etch process for dual...

Details Combined resist strip and barrier etch process for dual... Combined resist strip and barrier etch process for dual...

2000-12-22

2003-02-11

Coleman, William David (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S700000

Reexamination Certificate

active

06518174

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of semiconductor-based devices. More particularly, the present invention relates to improved techniques for fabricating semiconductor-based devices with dual damascene structures.
In semiconductor-based device (e.g., integrated circuits or flat panel displays) manufacturing, dual damascene structures may be used in conjunction with copper conductor material to reduce the RC delays associated with signal propagation in aluminum based materials used in previous generation technologies. In dual damascene, instead of etching the conductor material, vias, and trenches may be etched into the dielectric material and filled with copper.
To facilitate discussion,
FIG. 1A
is a cross-sectional view of a stack
100
on a wafer
110
used in the damascene process of the prior art. A contact
104
may be placed in a dielectric layer
108
over a wafer
110
. A barrier layer
112
, which may be of silicon nitride or silicon carbide, may be placed over the contact
104
to prevent the copper diffusion. A via level dielectric layer
116
may be placed over the barrier layer
112
. A trench stop layer
120
(silicon carbide or silicon nitride) may be placed over via level dielectric
116
. A trench level dielectric layer
124
may be placed over the trench stop layer
120
. An ARC layer
128
may be placed over the trench dielectric layer
124
. A patterned resist layer
132
may be placed over the hard mask layer
128
. The via level dielectric layer
116
and the trench level dielectric layer
124
may be formed from a low dielectric constant OSG material. The trench etch stop layer
120
and ARC layer
128
may be formed from (silicon carbide or silicon nitride for trench stop layer and SiON for ARC layer).
FIG. 2
is a high level flow chart of a process used in the prior art to form the stack
100
into dual damascene structure. The stack
100
may be subjected to an etch, which etches a via
140
down to the barrier layer
112
(step
204
). The etching of the via
140
may form a crust
144
which forms sidewalls. The crust
144
and resist
132
may be removed and repatterned to form a new resist layer
160
, which is patterned to form a trench (step
208
), as shown in FIG.
1
C. The stack may be subjected to an etch, which etches a trench
164
down to the trench etch stop layer
120
(step
212
), as shown in FIG.
1
D. The etching of the trench
164
may cause part of the via level dielectric layer
116
to facet
172
. This faceting may be considered as damage to the dual damascene structure. The etching of the trench
164
may also form a new crust
168
, which forms sidewalls. The stack
100
may then be subjected to a barrier layer etch (step
216
), which opens the via
140
to the copper contact
104
, as shown in FIG.
1
E. Removal of the barrier material of the barrier layer
112
is a challenge considering the poor selectivities between conventional dielectric materials and barrier materials. The resist layer
160
and crust
168
may then be stripped (step
220
), to provide the structure shown in FIG.
1
F.
It is desirable to provide an efficient etching process with minimal structure damage.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and in accordance with the purpose of the present invention for etching a stack. Generally, a trench patterned resist layer is placed over a dielectric layer of the stack. A trench is partially etched into the dielectric layer. A simultaneous stripping of the trench patterned resist layer, etching the barrier layer, and etching the trench is then performed. As a result an etch stack may be provided with less damage.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.


REFERENCES:
patent: 6083822 (2000-07-01), Lee
patent: 6123088 (2000-09-01), Ho
patent: 6184128 (2001-02-01), Wang et al.
patent: 6235653 (2001-05-01), Chien et al.
U.S. patent application No. 09/746,901, Entitled “Method of Preventing Damage to Organo-Silicate-Glass Materials during Resist Stripping”, Filed Dec. 22, 2000, Inventor(s): Annapragada.
U.S. patent application No. 09/746,900, Entitled “Method of Etching with NH3 and Fluorine Chemistries”, Filed Dec. 22, 2000, Inventor(s): Annapragada et al.

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