Combined in-situ high density plasma enhanced chemical vapor dep

Details Combined in-situ high density plasma enhanced chemical vapor dep Combined in-situ high density plasma enhanced chemical vapor dep

1998-03-19

1999-08-31

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

H01L 21316

Patent

active

059465921

ABSTRACT:
A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a highest etching/depositing component ratio and thus the lowest CMP removal rate; (c) forming a third HDP-CVD layer on the second HDP-CVD layer using the same HDP-CVD process but with a third HDP-CVD composition having a low etching/depositing component ratio and thus a high CMP removal rate; and (d) using a chemical mechanical process to remove at least a part of the third HDP-CVD layer using the second HDP-CVD layer as a stopper. All the three HDP-CVD compositions contain the same etching and silicon-containing deposition components so as to improve the CMP efficiency without incurring substantially increased fabrication cost.

REFERENCES:
patent: 5494854 (1996-02-01), Jain
Wang, Justin, "Advanced Techniquies for interlayer dielctric depostion and planarization", SPIE vol. 2090 Multilevel Interconnection (1993) pp. 85-92,. 1993.

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