Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2003-07-29
2004-11-09
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189020, C365S189050, C365S189120
Reexamination Certificate
active
06816420
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of serially programmable devices, and in particular to a method and apparatus for incorporating column redundancy into a serially programmable device.
BACKGROUND OF THE INVENTION
To reduce pin count in an integrated circuit (IC), serial programming is often used. Because serial programming data is loaded into the IC in a continuous stream, only a single data input pin is required for programming. Typically, the programming data is loaded into a shift register within the IC.
FIG. 1
shows a cascaded shift register
100
that has a typical register structure for a serially programmable IC. Shift register
100
includes flip flops
111
,
112
,
113
, and
114
, each of which includes an input terminal D, an output terminal Q, and a clock terminal CK. Output terminal Q of flip flop
111
is connected to input terminal D of flip flop
112
, output terminal Q of flip flop
112
is connected to input terminal D of flip flop
113
, and output terminal Q of flip flop
113
is connected to input terminal D of flip flop
114
to form the cascaded structure. Meanwhile, each clock terminal CK of flip-flops
111
-
114
is coupled to receive a clock signal CLOCK.
on each pulse of clock signal CLOCK, an input data value DIN is loaded into flip flop
111
, the data previously stored in flip flop
111
is loaded into flip flop
112
, the data previously stored in flip flop
112
is loaded into flip flop
113
, and the data previously stored in flip flop
113
is loaded into flip flop
114
. The data previously stored in flip-flop
114
is provided as an output data value DOUT. In this manner, serial data is shifted into (and out of) shift register
100
. The data stored in shift register
100
can also be read out in parallel from the output terminal Qs of each of flip flops
111
-
114
, as data values Q
1
-Q
4
, respectively.
Serially programmed memory ICs use this serial-in-parallel-out (SIPO) capability of a cascaded shift register to improve programming efficiency. In a typical non-volatile memory IC such as an electrically erasable programmable read only memory (EEPROM) or a FLASH memory, programming an individual memory cell in a memory array (typically using Fowler-Nordheim tunneling and/or channel hot electron injection) takes much longer than shifting data into a shift register. For example, 14 ms might be required to program a memory cell in an EEPROM or FLASH memory (using Fowler-Nordheim tunneling). In contrast, filling a shift register with new data only requires a number of clock cycles equal to the number of flip flops in the shift register—e.g., if the system clock is running at 22 MHz and the shift register is a 4096-bit shift register, filling the shift register would only require 0.19 ms (=4096/22×10
6
) Therefore, to minimize programming time, serial data is shifted into the shift register, and the contents of the shift register are then programmed into a particular address of the memory array as a single word. Since the memory cell programming for an entire row of the memory array can be performed in parallel, this “page mode” programming technique can significantly reduce overall programming time.
FIG. 2
shows a conventional serially programmable memory IC
200
that includes an input terminal
201
, a register output terminal
202
, a data register
210
connected between input terminal
201
and register output terminal
202
, a bitline latch
211
, a M×N memory array
220
, sense amplifiers
231
, a data latch
232
, a bit shifting multiplexer
233
, and an output terminal
203
. M×N memory array
220
is made up of M rows (i.e., rows W
0
through WM-
1
) and N columns (i.e., columns C
0
through CN-
1
) of memory cells. To program a row of memory array
220
, a programming bitstream DIN is shifted into data register
210
via input terminal
201
. Data register
210
provides a serial programming path for IC
200
—i.e., a data path into which a programming bitstream can be serially loaded, prior to a parallel programming operation. Once data register
210
is filled, the stored bitstream is loaded into bitline latch
211
, after which the latched data is programmed into a selected row of memory array
220
in a page mode programming operation. To read out a word from memory array
220
, the selected word data is latched into data latch
232
via sense amplifiers
231
, and the latched data is then shifted out of output terminal
203
as a serial output data stream DOUT by bit shifting multiplexer
233
. In this manner, the number of data input and output pins required by IC
200
can be minimized.
However, as memory arrays continue to increase in size, the denser memory structures become more susceptible to memory defects (such as a column short, bad trace, etc.). Therefore, to maintain a high production yield, it becomes increasingly desirable to provide redundancy in a memory array—i.e., include extra columns that can be used to replace defective columns. In the absence of such redundancy, a single bad memory cell can render an entire memory array unusable. Conventionally addressed memory arrays incorporate such redundant columns by simply addressing the appropriate redundant column instead of the defective column. However, in conventional serially programmable memory arrays, this type of random access is not available, making redundancy extremely difficult to incorporate.
For example, in
FIG. 2
, columns CN-
1
and CN-
2
could be redundant columns to be used if there are defects in any of columns C
0
through CN-
3
(which would then represent the “primary memory region” of memory array
220
—i.e., the portion of memory array
220
in which data would be stored in the absence of array defects). In such an arrangement, replacing a defective column with column CN-
1
would require that the flip flop in data register
210
associated with column CN-
1
receive the data originally intended for the flip flop associated with the defective column. However, the flip-flops in a shift register (i.e., data register
210
) are hardwired in a predetermined order, and so cannot be easily reordered to incorporate the redundant column in place of the defective column.
To overcome this limitation, conventional ICs sometimes include redundancy logic that counts clock cycles as data is shifted into the shift register. The redundancy logic uses the clock counts to determine whether a particular data bit is associated with a defective column, and if so, transfers that data bit to a redundant column. To function properly, this type of redundancy logic must know exactly when the program data begins shifting into the data register. However, in many cases, such program data timing knowledge is not available, so that conventional redundancy logic cannot be used.
For example, many modern ICs use the industry standard JTAG (Joint Test Action Group) interface for programming purposes. JTAG refers to IEEE standard 1149.1-1990 (includes IEEE Std 1149.1a-1993), published by the Institute of Electrical and Electronics Engineers, Inc. on Oct. 21, 1993 under ISBN 1-55937-350-4, herein incorporated by reference. IEEE standard 1149.1 defines a boundary scan test method for detecting bad connections (shorted pins, open pins, bad traces, etc.) in circuit boards. The JTAG interface includes a test data input (TDI) pin for loading serial test data into the data register of an IC, and this TDI pin is often used as a serial programming interface on many ICs. For example, input terminal
201
could represent a TDI pin in a JTAG-programmable IC (and register output pin could represent a TDO (test data output) pin to pass data out from data register
210
).
Because conventional JTAG-based programming methods involve continuously shifting the programming data through multiple daisy-chained ICs (i.e., the TDO pin of an IC being connected to the TDI pin of a subsequent IC), none of the individual ICs has knowledge of when its own program data is being loaded into its shift register. Only when program data has filled th
Bajwa Asim A.
Liu Ping-Chen
Dinh Son T.
Kubodera John
Liu Justin
Xilinx , Inc.
Young Edel M.
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