CMOS transistor with high drive current and low sheet...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257SE21634, C257SE21438, C257SE21439, C438S264000

Reexamination Certificate

active

07348248

ABSTRACT:
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate dielectric over a substrate, a gate electrode over the gate dielectric, a slim gate spacer along a side of the gate electrode, and a source/drain region substantially aligned with an edge of the slim gate spacer. The source/drain region includes a first implantation region having an overlap with the gate electrode, a second implantation region further away from the channel region than the first implantation region, and a third implantation region further away from the channel region than the second implantation region. The source/drain region preferably further comprises an epitaxy region spaced apart from the slim gate spacer.

REFERENCES:
patent: 5444282 (1995-08-01), Yamaguchi et al.
patent: 5719425 (1998-02-01), Akram et al.
patent: 5869879 (1999-02-01), Fulford et al.
patent: 5949105 (1999-09-01), Moslehi
patent: 6187641 (2001-02-01), Rodder et al.
patent: 6252277 (2001-06-01), Chan et al.
patent: 6258680 (2001-07-01), Fulford, Jr. et al.
patent: 6348390 (2002-02-01), Wu
patent: 6524938 (2003-02-01), Tao et al.
patent: 6713357 (2004-03-01), Wang et al.
patent: 6774409 (2004-08-01), Baba et al.
patent: 7105413 (2006-09-01), Nahm et al.
patent: 7132719 (2006-11-01), Koh
patent: 2003/0098486 (2003-05-01), Sambonsugi et al.
patent: 2004/0173815 (2004-09-01), Yeo et al.
patent: 2004/0175872 (2004-09-01), Yeo et al.
patent: 2004/0195646 (2004-10-01), Yeo et al.
Chidambaram, P.R., et al., “35% Drive Current Improvement from Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOS,” 2004 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pp. 48-49.
Ghani, T., et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,” IEDM, 2003, pp. 978-980.
Shimizu, A., et al., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement,” IEDM, 2001, pp. 433-436.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

CMOS transistor with high drive current and low sheet... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS transistor with high drive current and low sheet..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS transistor with high drive current and low sheet... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3978420

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.