CMOS silicide metal gate integration

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C257SE21199, C257SE21200, C438S649000, C438S651000, C438S655000, C438S664000, C438S682000

Reexamination Certificate

active

07655557

ABSTRACT:
The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

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Oh, J. et al. “Interdigitated Ge p-i-n Photodetectors Fabricated on a Si Substrate Using Graded SiGe Buffer Layers.” IEEE Journal of Quantum Electronics, vol. 38, No. 9 (2002).
Jones, R.E., et al., Fabrication and Modeling of Gigahertz Photodetectors in Heteroepitaxial Ge-on-Si Using a Garded Buffer Layer Deposited by Low Energy Plasma Enhanced CVD.: IEDM p. 793 (2002).
“Self Alligned Technique Employing Planarized Resist for Reducing Poly-Silicon Sheet Resistance by Formation of a Metal Silicide.” IBM Technical Disclosure Bulletin, IBM Corp., vol. 30, No. 5 (1987).

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