Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-01-28
1999-10-05
Dang, Trung
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438218, 438225, 438227, H01L 218238
Patent
active
059638028
ABSTRACT:
This invention proposes a process to form planarized twin-wells for CMOS devices. After depositing a pad oxide and a silicon nitride layers, a high-energy phosphorus ion implantation is performed to form the N-well by using a photoresist as s mask. A thick oxide layer deposited by liquid phase deposition process is then grown on the N-well region part of the silicon nitride layer, but not on the photoresist. After stripping the photoresist, a high-energy boron ion implantation is carried out to form the P-well by using the LPD-oxide layer as a mask. The thick LPD-oxide layer is removed by BOE or HF solution. A high temperature steam oxidation is performed to grow field oxides. The dopants are activated and driven in to form twin-wells at this step. After removing the pad oxide and the silicon nitride layer, the CMOS device is fabricated by standard processes.
REFERENCES:
patent: 5024961 (1991-06-01), Lee et al.
patent: 5362670 (1994-11-01), Iguchi et al.
patent: 5525535 (1996-06-01), Hong
patent: 5747368 (1998-05-01), Yang et al.
patent: 5773335 (1998-06-01), Chao
patent: 5854101 (1998-12-01), Wu
Douglas C.H. Yu et al., Low Threshold Voltage CMOS Devices with Smooth Topography for 1 Volt Applications, 1994 IEEE, pp. 489-492.
C.T. Liu et al., 0.2-.mu.m n-Channel and p-Channel MOSFET's Integrated on Oxidation-Planarized Twin-Tubs, IEEE Electron Device Letters, vol. 17, No. 11, Nov. 1996, pp. 500-502.
Ching-Fa Yeh et al., The Physiochemical Properties and Growth Mechanism of Oxide (SiO.sub.2 -.sub.x F.sub.x) by Liquid Phase Deposition with H.sub.2 O Addition Only, J. Electrochem. Soc., vol. 141, No. 11, Nov. 1994, pp. 3177-3181.
Dang Trung
Texas Instruments - Acer Incorporated
LandOfFree
CMOS process for forming planarized twin wells does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with CMOS process for forming planarized twin wells, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS process for forming planarized twin wells will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1182475