Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-12-19
1999-10-05
Brown, Peter Toby
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438174, 438194, 438199, 438232, 438289, 438291, H01L 218238
Patent
active
059638010
ABSTRACT:
A retrograde well in a CMOS device is formed by using a low energy ion implanter. Dopant atoms are implanted into a bare surface of the device's substrate, in a direction that is orthogonal to the surface of the substrate (for a substrate having a <100> orientation). The well implant can be performed at an energy below 220 keV. Chained implants for a punch-through barrier in the retrograde well can be performed after the well implant. When the substrate is annealed, the punch-through barrier is activated at the same time as the retrograde well.
REFERENCES:
patent: 3925107 (1975-12-01), Gdula et al.
patent: 5384279 (1995-01-01), Stolmeijer et al.
patent: 5399895 (1995-03-01), Koga
patent: 5404042 (1995-04-01), Okumura et al.
patent: 5405790 (1995-04-01), Rahim et al.
patent: 5416038 (1995-05-01), Hsue et al.
patent: 5492845 (1996-02-01), Fujimaki
patent: 5693505 (1997-12-01), Kobayashi
patent: 5693976 (1997-12-01), Chao
patent: 5747368 (1998-05-01), Yang et al.
patent: 5795803 (1998-08-01), Takamura et al.
Aronowitz Sheldon
Khan Laique
Kimball James
Brown Peter Toby
LSI Logic Corporation
Pham Long
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