CMOS optimization method utilizing sacrificial sidewall spacer

Details CMOS optimization method utilizing sacrificial sidewall spacer CMOS optimization method utilizing sacrificial sidewall spacer

1998-04-29

2000-07-25

Chaudhuri, Olik

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438303, 257392, H01L 218238

Patent

active

060935944

ABSTRACT:
An ultra-large scale CMOS integrated circuit semiconductor device is processed after the formation of the gates and gate oxides by N-type dopant implantation to form N-type shallow source and drain extension junctions. Spacers are formed for N-type dopant implantation to form N-type deep source and drain junctions. A higher temperature rapid thermal anneal then optimizes the NMOS source and drain extension junctions and junctions, and the spacers are removed. A thin oxide spacer is used to displace P-type dopant implantation to P-type shallow source and drain extension junctions. A nitride spacer is then formed for P-type dopant implantation to form P-type deep source and drain junctions. A second lower temperature rapid thermal anneal then independently optimizes the PMOS source and drain junctions independently from the NMOS source and drain junctions.

REFERENCES:
patent: 5766991 (1998-06-01), Chen
patent: 5869866 (1999-02-01), Fulford, Jr. et al.
patent: 5920104 (1999-07-01), Nayak et al.
patent: 5952693 (1999-09-01), Wu

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