CMOS device having retrograde n-well and p-well

Details CMOS device having retrograde n-well and p-well CMOS device having retrograde n-well and p-well

2005-11-22

2005-11-22

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S372000, C257S391000, C257S392000, C257S402000

Reexamination Certificate

active

06967380

ABSTRACT:
A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.

REFERENCES:
patent: 4558508 (1985-12-01), Kinney et al.
patent: 4613885 (1986-09-01), Haken
patent: 4929565 (1990-05-01), Parrillo
patent: 5138420 (1992-08-01), Komori et al.
patent: 5304833 (1994-04-01), Shigeki et al.
patent: 5384279 (1995-01-01), Stolmeijer et al.
patent: 5413945 (1995-05-01), Chien et al.
patent: 5494843 (1996-02-01), Huang
patent: 5736416 (1998-04-01), Johansson
patent: 5792680 (1998-08-01), Sung et al.
patent: 5814866 (1998-09-01), Borland
patent: 5963799 (1999-10-01), Wu
patent: 6144076 (2000-11-01), Puchner et al.
patent: 6157064 (2000-12-01), Huang
patent: 6235568 (2001-05-01), Murthy et al.
patent: 6258641 (2001-07-01), Wong et al.
patent: 6271551 (2001-08-01), Schmitz et al.
patent: 6300819 (2001-10-01), De et al.
patent: 6312981 (2001-11-01), Akamatsu et al.
patent: 6329260 (2001-12-01), DeJong et al.
patent: 6417547 (2002-07-01), Kang
patent: 6462385 (2002-10-01), Kumagai
patent: 3-99430 (1991-04-01), None
W.S. Johnson, “Multiple Masking Technique In Ion Implantation”, IBM TDB vol. 15, No. 2 Jul. 1972, pp. 660-661.

Affiliated with

Also associated with

Rating

CMOS device having retrograde n-well and p-well does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS device having retrograde n-well and p-well, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS device having retrograde n-well and p-well will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3455330