Clipped sine shaped waveform to reduce the cycling-induced elect

Details Clipped sine shaped waveform to reduce the cycling-induced elect Clipped sine shaped waveform to reduce the cycling-induced elect

1997-05-15

1998-03-10

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular biasing

36518529, 365218, G11C 1606

Patent

active

057269335

ABSTRACT:
The present invention provides method to erase and program flash EEPROMS devices using a clipped sine waveform (Vg). The clipped sine waveform reduces the tunneling oxide electric field between the floating gate and the source or drain region thereby reducing electron trapping. The method for the erase cycle comprises: applying a positive voltage to a source region; grounding a well region; floating the drain region; and simultaneously applying a negative clipped sine waveform voltage to a control gate during the erase cycle. The program cycle of the invention comprises: applying a voltage to a drain region; grounding a well region; floating a source region; and simultaneously applying a clipped sine waveform voltage to the control gate whereby the clipped sine waveforms reduce the electric field in a tunnel oxide layer which reduces the electron trapping.

REFERENCES:
patent: 5042009 (1991-08-01), Kazerounian et al.
patent: 5410511 (1995-04-01), Michiyama
patent: 5485423 (1996-01-01), Tang et al.
patent: 5526315 (1996-06-01), Kaya et al.
patent: 5568439 (1996-10-01), Harari
patent: 5600592 (1997-02-01), Atsumi et al.

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