Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-04-06
2000-10-10
Smith, Matthew
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438226, 438283, 438594, H01L 21336, H01L 213205
Patent
active
061301329
ABSTRACT:
The following steps are used to form a split gate electrode MOS FET device. Form a tunnel oxide layer over a semiconductor substrate. Over the tunnel oxide layer, form a doped first polysilicon layer with a top surface upon which a native oxide forms. Then as an option, remove the native oxide layer. On the top surface of the first polysilicon layer, form a silicon nitride layer and etch the silicon nitride layer to form it into a cell-defining layer. Form a polysilicon oxide dielectric cap over the top surface of the first polysilicon layer. Aside from the polysilicon oxide cap, etch the first polysilicon layer and the tunnel oxide layer to form a floating gate electrode stack in the pattern of the masking cap forming a sharp peak on the periphery of the floating gate electrode. Form spacers on the sidewalls of the gate electrode stack. Then form blanket inter-polysilicon dielectric and blanket control gate layers covering exposed portions of the substrate and covering the stack. Pattern the inter-polysilicon dielectric and control gate layers into a split gate electrode pair. Form a source region self-aligned with the floating gate electrode stack; perform a tungsten silicide anneal; and form a drain region self-aligned with the control gate electrodes.
REFERENCES:
patent: 4868629 (1989-09-01), Eitan
patent: 5349220 (1994-09-01), Hong
patent: 5408115 (1995-04-01), Chang
patent: 5422301 (1995-06-01), Otsuki
patent: 5445999 (1995-08-01), Thakur et al.
patent: 5478767 (1995-12-01), Hong
patent: 5480819 (1996-01-01), Huang
patent: 5492854 (1996-02-01), Ando
patent: 5614747 (1997-03-01), Ahn et al.
patent: 5915178 (1999-06-01), Chiang et al.
patent: 5939333 (1999-08-01), Hurley et al.
patent: 5940706 (1999-08-01), Sung et al.
Hsieh Chia-Ta
Kuo Di-Son
Lin Yai-Fen
Sung Hung-Cheng
Ackerman Stephen B.
Jones, II Graham J.
Malsawma Lex H
Saile George O.
Smith Matthew
LandOfFree
Clean process for manufacturing of split-gate flash memory devic does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Clean process for manufacturing of split-gate flash memory devic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clean process for manufacturing of split-gate flash memory devic will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2255994