Circuit for controlling isolation transistors in a semiconductor

Details Circuit for controlling isolation transistors in a semiconductor Circuit for controlling isolation transistors in a semiconductor

1993-11-24

1995-03-07

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

365205, 36523003, 36523008, G11C 700

Patent

active

053964659

ABSTRACT:
A semiconductor memory device has adjacent memory arrays and isolation transistors disposed between a common bit sense amplifier and the memory arrays. An isolation control circuit according the present invention generates the power supply voltage Vcc (not the boost voltage Vpp) during the burn-in mode of operation, so that the gate oxide layer of the isolation transistors is prevented from being destroyed or deteriorated.

REFERENCES:
patent: 4974206 (1990-11-01), Iyama
patent: 5016224 (1991-05-01), Tanaka
patent: 5105384 (1992-04-01), Noguchi
patent: 5267214 (1993-11-01), Fujishima

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