Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
1999-12-17
2002-05-28
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S101000, C326S049000
Reexamination Certificate
active
06396300
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to electronic devices and, more specifically, to a circuit and method for isolating a contact pad from a logic circuit.
BACKGROUND OF THE INVENTION
Processed semiconductor wafers typically comprise an array of substantially isolated integrated circuitry locations, which are subsequently separated to form semiconductor dies. In order to test the operability of the integrated circuitry of a die location on a wafer, a wafer probe card is applied to each die location. The wafer probe card includes a series of pins that are placed in physical contact with a die location's contact pads, which in turn connect to the die location's circuitry. The pins apply voltages to the input contact pads and measure the resulting output electrical signals from the output contact pads. However, the wafer probe card's pins may not be able to extend to all of the contact pads. As a result, it is necessary to provide accessible redundant contact pads on the die location and couple them to particular logic circuits.
An additional hardware limitation relevant to testing the die locations is the spacing between the pins of the wafer probe card. Specifically, the pins may be spaced further apart than the contact pads in a particular area of a die location. As a result, one contact pad in that area may not be serviceable by a pin. As a solution, prior art teaches providing a redundant contact pad in another area of the die location that can be reached by a pin. This redundant pad is connected to the same logic circuit as the unserviceable contact pad.
There may also be other reasons for including additional contact pads on a die. Regardless of the reasons, prior art allows these redundant contact pads to remain connected to the logic circuit after they are no longer needed. By remaining connected, these redundant contact pads contribute additional capacitance to their associated logic circuits and thereby degrade performance of the die.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a circuit for isolating a contact pad from a logic circuit. In a first exemplary embodiment, a complementary metal-oxide semiconductor (CMOS) multiplexer connects a redundant pad to a logic circuit, wherein the CMOS multiplexer is controlled by a fuse. Programming the fuse disables the multiplexer and prevents the redundant contact pad from affecting the logic circuit. Thus, this embodiment has the advantage of removing a parasitic component that might degrade performance of the logic circuit.
In a second exemplary embodiment, one fuse circuit controls several multiplexers, wherein each multiplexer services a separate logic circuit. This embodiment offers the advantage of reducing capacitance of several logic circuits while simultaneously conserving the die space needed to do so.
In a third exemplary embodiment, one fuse circuit controls two multiplexers, wherein both multiplexers service the same logic circuit. In addition to interposing a first multiplexer between the redundant contact pad and the logic circuit, a second multiplexer is interposed between a main contact pad and the logic circuit. Further, this second multiplexer is configured to operate conversely to the first multiplexer. Thus, before the fuse is programmed, only the redundant contact pad is in electrical communication with the logic circuit. After the fuse is programmed, only the main contact pad is in electrical communication with the logic circuit. The advantage offered by this embodiment is that, while one contact pad is being used, the other contact pad does not contribute additional capacitance.
A fourth exemplary embodiment combines the features described in the second and third exemplary embodiments. Thus, not only does one fuse control the electrical communication of several logic circuits, but the fuse also controls which contact pad can be used with each logic circuit. Accordingly, this embodiment combines the advantages found in the second and third embodiments. A fifth embodiment achieves the same advantages discussed above using an anti-fuse in place of the fuse. In addition, all of the embodiments listed above provide capacitance-reducing advantages while avoiding accidental programming of the fuse due to an ESD event.
Moreover, a sixth exemplary embodiment replaces the fuse controlled multiplexer with the fuse itself for linking the redundant contact pad with the logic circuit. In doing so, this embodiment offers all of the capacitance-reducing advantages of the embodiments discussed above and takes up less die space.
In a seventh exemplary embodiment, an isolation circuit is used during a test mode to connect a logic circuit to a no-connect pin on an integrated device, thereby providing the advantage of having an additional access point for testing the integrated device. Once the test mode has ended, the fusing element is programmed and the no-connect pin electrically disconnects from the logic circuit.
In an eighth exemplary embodiment, a die is provided having two groups of contact pads, wherein each group is configured to accommodate a different lead frame. One contact pad from each group is connected to a particular logic circuit. An isolation circuit similar to the fourth exemplary embodiment is provided to regulate electrical communication with the contact pads. Specifically, in an unprogrammed state, the isolation circuit electrically isolates the second group of contact pads from the logic circuits. The first group remains in electrical communication with the logic circuits and may accommodate an appropriate lead frame. If, on the other hand, a lead frame is chosen that is compatible with the second group of contact pads, then the entire first group
64
can be isolated in a single programming step that also serves to enable communication between the entire second group
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and the logic circuits. This embodiment has the advantage of providing a die that is compatible with two different types of lead frames. In addition, the adaptation requires at most one programming step. As a further advantage, this embodiment restricts additional capacitance from unneeded contact pads once the appropriate lead frame has been determined.
A ninth exemplary embodiment is configured in a manner similar to the eighth embodiment. Rather than including one all-encompassing isolation circuit, however, this embodiment includes several isolation circuits—one for each logic circuit. Each isolation circuit resembles the third exemplary embodiment in that the isolation circuit can be used to determine which contact pad communicates with the logic circuit—either the pad from the first group or the pad from the second group. By allowing a programming choice for each logic circuit, this embodiment provides a die that can adapt to other lead frames in addition to the two lead frames addressed in the eighth embodiment. Accordingly this embodiment also restricts additional capacitance from unneeded contact pads once the appropriate lead frame has been determined.
In addition to these circuit embodiments, the present invention encompases various methods for achieving these advantages.
REFERENCES:
patent: 4533841 (1985-08-01), Konishi
patent: 5107208 (1992-04-01), Lee
patent: 5272365 (1993-12-01), Nakagawa
patent: 5402390 (1995-03-01), Ho et al.
patent: 5517455 (1996-05-01), McClure et al.
patent: 5526317 (1996-06-01), McClure
patent: 5726585 (1998-03-01), Kim
patent: 5859442 (1999-01-01), Manning
patent: 5929691 (1999-07-01), Kim et al.
Loughmiller Daniel R.
Porter Stephen R.
Brantley Charles
Micro)n Technology, Inc.
Tran Anh Q.
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