Circuit and method for an open bit line memory cell with a verti

Details Circuit and method for an open bit line memory cell with a verti Circuit and method for an open bit line memory cell with a verti

1998-08-24

2000-12-26

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438587, H01L 218242

Patent

active

061658367

ABSTRACT:
A memory cell. The memory cell includes an access transistor. The access transistor is formed in a pillar of single crystal semiconductor material. The transistor has first and second source/drain regions and a body region that are vertically aligned. The memory cell also includes a body contact that is coupled to the body region. A gate of the transistor is disposed on a side of the pillar that is opposite from the body contact. A trench capacitor is also included. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide. An insulator layer that separates the access transistor and the trench capacitor from an underlying layer of semiconductor material.

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