Chip-size package (CSP) using a multi-layer laminated lead frame

Details Chip-size package (CSP) using a multi-layer laminated lead frame Chip-size package (CSP) using a multi-layer laminated lead frame

1997-08-01

1999-04-13

Kincaid, Kristine

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

174 524, 257676, 257693, 257738, 257778, 257787, H01L 2328

Patent

active

058941070

ABSTRACT:
A method for manufacturing a chip-size package and the chip-size package produced by the method uses first and second lead frames which are prepared by a stamping process. The first lead frame has leads with receiving parts, and the leads are integrally formed with lengthwise side rails of the lead frame. The second lead frame has external connections which align with the receiving parts of the leads when the second lead frame is positioned on top of the first lead frame and attached thereto. Guide holes located on the crosswise side rails of both lead frames can be used to easily align the two lead frames. A semiconductor chip is then adhered to the underside of the first lead frame, and the bonding pads of the semiconductor chip are electrically connected to the leads of the first lead frame. Then the two lead frames and the chip are encapsulated, with only the external connections of the second lead frame remaining exposed to the outside. Solder balls are then attached to the external connections for mounting onto a substrate. This chip-size package is inexpensive to produce, because the first and second lead frames can be produced by a stamping process, which is less complex and cheaper than the conventional half-etching process.

REFERENCES:
patent: 5157480 (1992-10-01), McShane et al.
patent: 5663594 (1997-09-01), Kimura
patent: 5668405 (1997-09-01), Yamashita
patent: 5677566 (1997-10-01), King et al.

Affiliated with

Also associated with

Rating

Chip-size package (CSP) using a multi-layer laminated lead frame does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Chip-size package (CSP) using a multi-layer laminated lead frame, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip-size package (CSP) using a multi-layer laminated lead frame will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-224054