Chip scale package with flip chip interconnect

Details Chip scale package with flip chip interconnect Chip scale package with flip chip interconnect

2002-02-22

2004-05-18

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S108000, C257S778000

Reexamination Certificate

active

06737295

ABSTRACT:

BACKGROUND
This invention relates to high performance semiconductor device packaging and, particularly, to chip scale packages having flip chip interconnection.
So-called chip scale packages have come into increasing use particularly, by virtue of their very small size, for packaging integrated circuit chips in handheld or portable electronic applications. Wire bonding has been the most widely used technique for interconnecting the input/output pads of the integrated circuit chip with the package.
Flip chip interconnection is considered a promising alternative to wire bonding, in view of the potential of flip chip interconnection to provide further decrease in the package size, and in view of the higher electronic performance that flip chip interconnection can provide.
Various techniques of flip chip interconnection have been proposed for use in chip scale packages. These include interconnection by solder reflow, and “particulate” interconnection easing anisotropic conductive adhesives “ACAs” or isotropic conductive adhesives “ICAs”. Each of these techniques presents challenges.
The technique of solder reflow interconnection inherently employs a melting and flow of the interconnect material, and this presents difficulties in forming interconnects at very fine geometries. In particular, as a practical matter currently the smallest interconnection pitch for solder reflow interconnection is of the order of 160 micrometers. It is desirable for very small size packaging to reliably form interconnects at finer geometries than this pitch permits.
In particulate interconnect techniques, whether ACAs or ICAs, conductive particles, such as particles of nickel, of a gold-coated polymer, or of silver, are held by mechanical pressure to form the interconnect. Generally, particulate interconnect structures are incapable of carrying high electrical currents, and they lack long-term reliability because of the particulate nature of the interconnection.
Chip scale packages employing flip chip interconnection generally are plagued by poor long-term reliability of the connections between the chip scale package and the printed circuit board to which they are attached to form the electronic subassembly, the so-called second level interconnections. This problem arises from the fact that the second level interconnections typically are located in the shadow of the integrated circuit chip, in order to achieve miniaturization. As a result of this configuration, there is a large mismatch in the effective coefficient of thermal expansion of the chip scale package and the printed circuit board, and this causes excessive stress in the interconnections and may eventually lead to failure of the interconnections by mechanical fatigue over time.
A chip scale package is desired that provides the advantages of flip chip interconnection while avoiding the disadvantages presented by conventional package configurations.
SUMMARY
According to the invention, a flip chip package features a solid-state bond technique for connecting the input/output pads on the integrated circuit chip and the package substrate. The solid-state bond technique involves a direct mating of metal surfaces, and does not employ any particulate conductive material. Accordingly the connections are capable of carrying very high current, and display good long-term reliability as compared to ACA or ICA particulate interconnects. Moreover the solid-state bond technique does not entail a melting or flow of any interconnecting material. Accordingly the connections can be formed at very fine geometries, typically as low as 70 micrometers pitch.
Also according to the invention, the space between the surface of the integrated circuit chip and the subjacent surface of the package substrate is filled with a patterned adhesive structure, which consists of one or more adhesive materials that are deployed in a specified pattern in relation to the positions of the second level interconnections between the package and the printed circuit board. According to this aspect of the invention, the coefficient of thermal expansion and the compliancy of the package structure in the regions overlying the second level connections can be tailored to reduce potentially damaging propagation of stress generated in the second level connections on the package to features on the integrated circuit chip, and thereby extending the long-term reliability of the package and of the interconnects.
In one general aspect, therefore, the invention features a flip chip package including an integrated circuit chip having interconnect bumps formed on input/output pads in a specified arrangement, and a package substrate having a plurality of bond pads in a complementary arrangement. The interconnect between the bumps on the integrated circuit chip and the respective bond pads on the package substrate is established by direct mating of the bump surfaces with the respective bond pads and thermo-mechanical deformation of the bumps. The thermo-mechanical process entails heating while forcing the bump against the pad.
In some embodiments the bump is constructed of a material or combination of materials selected to provide low yield strength, high ductility, and an oxidation- and corrosion-resistant surface. In some embodiments the bumps are formed of gold or a gold alloy. In some embodiments the bumps are formed on the input/output pads of the integrated circuit chip by a “stud bumping” or a “solder bumping” or an electroplating process,
In another general aspect, the invention features a method for forming a flip chip package, by: providing an integrated circuit chip having interconnect bumps formed on input/output pads in a specified arrangement, each interconnect bump having low yield strength, high ductility, and an oxidation- and corrosion-resistant surface; providing a package substrate having a plurality of bond pads in an arrangement complementary to the specified arrangement of input/output pads on the integrated circuit chip; contacting the bumps with the respective bond pads on the package substrate; and thermo-mechanically treating the bumps to form solid-state connections of the bumps with their respective bond pads.
In some embodiments, the thermo-mechanically treating step includes concurrently heating and applying a force between the bumps and the pads. Usually the bump and pad are heated to a temperature in the range about 150° C. to about 300° C., typically about 240° C. for a gold bump; and the force is provided by weighting with a mass in the range about 25 grams to about 150 grams per bump, typically about 50 grams per bump for gold bumps.
In another general aspect, the invention features a flip chip package configured for second level interconnection to a printed circuit board by way of interconnect structures formed in the shadow of the chip. According to this aspect of the invention, a flip chip package includes an integrated circuit chip having interconnect bumps formed on input/output pads in a specified arrangement in a surface of the chip, and a package substrate having a plurality of bond pads in a complementary arrangement in a subjacent surface of the package substrate. In preferred embodiments the chip-to-package interconnect bumps are bonded to the respective bonding pads in a solid-state manner. Second level interconnect sites are arranged in a second surface of the package substrate, and second level interconnect structures are connected to the respective second level interconnect sites. Between the integrated circuit chip and the package substrate is a fill volume, which is at least partly filled with one or more fill materials each having a selected specific elastic modulus, including a lower elastic modulus material in regions of the fill volume that overlie the second level interconnect sites.
In some embodiments, the fill volume includes a first fill zone made up of a plurality of generally columnar volumes, generally overlying the plurality of second level interconnect sites, and the second fill zone constituting the remainder of the fill volume. In some emb

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