Chip scale package and method for manufacture thereof

Details Chip scale package and method for manufacture thereof Chip scale package and method for manufacture thereof

1997-07-08

2000-10-31

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

257698, 257702, 257703, H01L 2348, H01L 2352, H01L 2940

Patent

active

061407089

ABSTRACT:
An assembly process provides a chip scale package (CSP) which characteristically includes (i) a perforated substrate in which vias can be embedded, (ii) a solder mask on which the integrated circuit die can be attached, and (iii) efficient use of the surface area for electrically routing signals from the integrated circuit die to the external terminals attached to the perforated substrate. The resulting package is highly compact and therefore has a foot print minimally larger than the surface area of the integrated circuit chip. Consequently, the costs of substrate and capsulation materials are minimized. The assembly process allows very high volume production because a large number of integrated circuits can be made on a single unit of the substrate, and singulation is performed in the assembly process at a stage much later than the corresponding stage in a conventional process.

REFERENCES:
patent: 4082394 (1978-04-01), Gedney et al.
patent: 4322778 (1982-03-01), Barbour et al.
patent: 5355283 (1994-10-01), Marrs et al.
Japanese patent laying-open publication No. Sho53-85373 (published on Jul. 27, 1978).

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