Chip package structure

Details Chip package structure Chip package structure

2006-06-13

2006-06-13

Quach, T. N. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With provision for cooling the housing or its contents

C257S717000, C257S777000

Reexamination Certificate

active

07061103

ABSTRACT:
A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is flip-chip bonded and electrically connected to the carrier or another chip. There is a flip-chip bonding gap between the chip and the carrier or other chips. A heat sink is positioned on the uppermost chip. The encapsulating material layer fills the flip-chip bonding gap as well as a gap between the uppermost chip and the heat sink. A part of the surface of the heat sink away from the upper-most chip is exposed. Furthermore, the encapsulating material layer is formed in a simultaneous molding process. For example, the chip is separated from the heat sink by a distance between 0.03˜0.2 mm, and the encapsulating material has a thermal conductivity greater than 1.2 W/m.K.

REFERENCES:
patent: 5471027 (1995-11-01), Call et al.
patent: 6610560 (2003-08-01), Pu et al.
patent: 6627997 (2003-09-01), Eguchi et al.
patent: 6734552 (2004-05-01), Combs et al.
patent: 6844622 (2005-01-01), Huang et al.
patent: 2003/0141582 (2003-07-01), Yang et al.

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